arXiv:2607. 17398v1 Announce Type: cross Abstract: Analytical placers rely on differentiable objective functions to guide placement, typically combining intermediate surrogate metrics such as half-perimeter wirelength (HPWL) and cell-density penalties.
arXiv:2608. 13790v1 Announce Type: cross Abstract: Macro placement significantly affects a chip's post-route performance, power, and area (PPA).
arXiv:2607. 16632v1 Announce Type: cross Abstract: Hardware engineering exposes coding agents to a form of long-horizon work that is difficult to capture with pass-at-k: progress is continuous, tool feedback is delayed and heterogeneous, and a backend failure may require revising RTL rather than tuning another physical-design parameter.
arXiv:2606. 08904v1 Announce Type: new Abstract: Macro placement is a fundamental step in modern chip physical design, playing a crucial role in determining the solution quality of high-dimensional combinatorial optimization problems.
Macro placement is a fundamental step in modern chip physical design, playing a crucial role in determining the solution quality of high-dimensional combinatorial optimization problems. Despite recent advancements in machine learning for spatial coordinate determination, the temporal dimension of placement sequencing remains largely governed by static heuristics.
QiMeng-ChipV-RTL is a multi‑agent framework that tackles the challenges of generating Register‑Transfer Level (RTL) code for industrial IP‑level hardware design. By partitioning long design documents into short, localized tasks and using hierarchical planning, localized code generation, interface‑consistent merging, and AST‑guided debugging, it scales to complex specifications. Experiments on the RealBench benchmark show ChipV-RTL achieves a 45.0% pass rate, outperforming state‑of‑the‑art LLMs and agents which reach only 21.6%.
arXiv:2606. 08976v1 Announce Type: new Abstract: LLM-based RTL generation and reasoning is a promising direction for hardware design automation.
TO-Agents is a multi‑agent AI framework that translates natural‑language design intent into iterative topology optimization. It converts a human problem description into solver inputs, runs the optimizer, renders 3D topologies, and employs a judge agent to critique and revise results using multiview vision‑language reasoning. Evaluated on a cantilever beam and a phone‑stand design, the system achieved preference‑aligned designs in 60% of trials, outperforming an ablated pipeline by up to six times and enabling end‑to‑end intent‑to‑prototype design with additive manufacturing.
arXiv:2606. 00131v1 Announce Type: cross Abstract: Post-link optimizers (PLOs) such as Propeller and BOLT have demonstrated that precise, profile-guided code layout can extract significant performance gains from heavily optimized binaries.
arXiv:2606. 15693v1 Announce Type: cross Abstract: LLMs have significantly advanced code generation, enabling the synthesis of functional programs.
arXiv:2608. 13767v1 Announce Type: new Abstract: Analog IC layout design remains a labor-intensive iterative process dominated by simulation-driven refinement.
arXiv:2606. 05680v1 Announce Type: cross Abstract: Recent advances in large language models (LLMs) have enabled the automatic synthesis (generation) of register-transfer level (RTL) code from natural language instructions, offering a promising pathway to accelerate chip design.