arXiv:2606. 15052v1 Announce Type: cross Abstract: Traditional design of analog circuits heavily relies on manual interventions across topology, sizing, and layout, with prior automation addressing stages in isolation.
arXiv:2608. 13767v1 Announce Type: new Abstract: Analog IC layout design remains a labor-intensive iterative process dominated by simulation-driven refinement.
arXiv:2607. 13416v1 Announce Type: new Abstract: Automating analog circuit topology design is essential to reduce the extensive manual effort required to meet increasingly diverse and customized application demands.
arXiv:2608. 13472v1 Announce Type: cross Abstract: Analog circuit design is a time-consuming, iterative process in a nonlinear and high-dimensional design space that relies heavily on expert intuition.
arXiv:2607. 14165v1 Announce Type: cross Abstract: While Large Language Models (LLMs) have demonstrated significant capability in software code generation, their application to analog Electronic Design Automation (EDA) is bottlenecked.
Analog circuit sizing remains a challenging and time-consuming task due to the large design space, strong performance trade-offs, and increasing circuit complexity in scaled technologies. Although rec...
ATLAS is an embedding‑guided quality‑diversity framework that enables scaffold‑free synthesis of full algorithms for combinatorial optimization using large language models. It allows the LLM to freely choose, restructure, and control algorithm components while automatically detecting and repairing execution, interface, and feasibility failures. Across four NP‑hard problems, ATLAS outperforms state‑of‑the‑art component‑synthesis methods and remains competitive with strong human‑designed algorithms, demonstrating that a larger design space can be practically searched.
arXiv:2606. 01188v1 Announce Type: cross Abstract: Translating natural-language hardware requirements into correct printed circuit board (PCB) schematics remains difficult in embedded, IoT, and wearable development.
arXiv:2609.07434v1 Announce Type: new Abstract: Natural-language Computer-Aided Design (CAD) code generation aims to turn design intent into executable and editable parametric programs. Large languag...
THEIA is a multimodal dataset that pairs thousands of analog circuit layout images with question‑answer conversations, and it introduces a benchmark using a fine‑tuned vision‑language model to analyze GDSII files. The dataset and benchmark enable designers to interact with and query physical layouts as intuitive, meaningful entities. Experiments on five realistic tasks show the fine‑tuned model outperforms general‑purpose vision‑language models by up to 73%, revealing a significant gap between general multimodal reasoning and domain‑specific layout understanding.
arXiv:2603. 24714v2 Announce Type: replace Abstract: Analog design often slows down because even small changes to device sizes or biases require expensive simulation cycles, and high-quality solutions typically occupy only a narrow part of a very large search space.
arXiv:2606. 30429v1 Announce Type: new Abstract: Text-to-3D systems can now synthesize a mechanical part from a single sentence, yet the result is a shape to render, not a design to edit.
PICasso is an AI‑enabled framework that converts natural‑language specifications into manufacturable silicon photonic integrated circuits (PICs) through a structured pipeline of NL → YAML → GDS, PDK‑aware knowledge injection, automated placement and routing, DRC/LVS validation, and SAX‑based photonic simulation. The authors introduce PIC‑Set, a benchmark of 36 parameterized PIC design tasks, and evaluate several large language models (LLMs) using new metrics such as structural and functional Spec@k, optimization efficiency, and robustness. Across the benchmark, PICasso markedly improves specification satisfaction, achieving up to 92.7% structural Spec@3 and 52% functional Spec@3, while reducing mean insertion loss from 4.98 dB to 3.25 dB through simulation‑guided optimization.