Deep Microcompression (DMC) is a hardware‑aware pipeline that combines structured pruning, quantization‑aware training, and fixed‑length bit‑packing to enable deep learning inference on bare‑metal microcontrollers. The method achieves a 55.8× weight compression on LeNet‑5 while maintaining 98.77% accuracy, and produces a dependency‑free C library with deterministic latency. On the RP2040 Cortex‑M0+ microcontroller, DMC cuts binary size threefold compared to TensorFlow Lite while matching its accuracy, and it is the first documented deployment of a standard CNN on the 2 KB SRAM ATmega328P.
arXiv:2610.15092v1 Announce Type: cross Abstract: Quantization plays a crucial role in efficiently deploying deep learning models on resource-constrained devices. Post-training quantization does not...
The paper presents a PyTorch-based framework for designing and optimizing binarized neural networks, incorporating freezing and pruning mechanisms. It introduces a novel pruning method that uses a global weighting scheme to assess parameter importance across abstraction levels, achieving a 70% pruning rate on VGG11 without sacrificing accuracy—outperforming existing binarized pruning results of 41%. The framework facilitates rapid, reproducible evaluation and prototyping of state‑of‑the‑art binarized network techniques.
The paper introduces W16A16, a 16‑bit precision quantization method for convolutional neural networks aimed at microcontroller units. On the Armv7E‑M architecture, W16A16 delivers faster inference speeds and lower energy consumption than existing quantization schemes while reducing quantization errors by roughly tenfold compared to 8‑bit approaches. The authors analyze the MCU architecture, explain why 16‑bit operations yield performance gains, and evaluate empirical errors and resource usage across regression and classification tasks.
Deep neural networks have witnessed remarkable advancements in recent years and have become integral to various applications. However, alongside these developments, training and deployment of neural network models on embedding and edge devices face significant challenges due to limited memory and computational resources.
arXiv:2606. 04063v1 Announce Type: cross Abstract: Deploying large language models (LLMs) is challenging due to their significant memory and computational requirements.
arXiv:2607. 06600v1 Announce Type: cross Abstract: Line segment detection is a key building block in visual SLAM, 3D reconstruction, and industrial inspection.
arXiv:2607. 28418v1 Announce Type: cross Abstract: Pruning is a promising approach for improving the efficiency of LLMs.
arXiv:2603. 15106v2 Announce Type: replace Abstract: Enabling efficient deep neural network (DNN) inference on edge devices with different hardware constraints is a challenging task that typically requires DNN architectures to be specialized for each device separately.
arXiv:2605. 24391v2 Announce Type: replace-cross Abstract: As the demand for deep learning grows, cost reduction through quantization has become essential for both training and inference.
The paper introduces REQAP, a reliability‑aware quantized weight packing technique for systolic‑array DNN accelerators. It uses a sensitivity‑driven mixed‑precision quantization to assign layer‑wise bit‑widths, a deterministic register‑level packing strategy for SIMD‑within‑a‑register execution, and selective bit‑level protection that replicates critical MSBs into unused register space. Experiments on AlexNet, VGG‑11, and ResNet‑18 show up to 62% memory reduction, 56% fewer MAC operations, and improved accuracy resilience under fault injection compared to baseline and fully protected models.
Squeeze10-LLM is a staged mixed‑precision post‑training quantization framework that reduces 16‑bit LLM weights to an average of 1.6 bits per weight by assigning 80% of weights to 1 bit and 20% to 4 bits. It introduces Post‑Binarization Activation Robustness (PBAR), a weight significance metric that considers activation impact, and Full Information Activation Supervision (FIAS), a strategy that preserves activation information to limit error propagation. Experiments on LLaMA and LLaMA2 demonstrate that Squeeze10‑LLM achieves state‑of‑the‑art performance for sub‑2‑bit weight‑only quantization, raising average accuracy from 43% to 56% on six zero‑shot classification tasks.
arXiv:2510.08999v2 Announce Type: replace-cross Abstract: Compressing large-scale neural networks is essential for deploying models on resource-constrained devices. Most existing methods adopt weight...