arXiv:2606. 16290v1 Announce Type: cross Abstract: Hardware-aware neural architecture search (HW-NAS) allows the integration of Convolutional Neural Networks (CNNs) in microcontrollers devices by automatically designing neural architectures that can fit prearranged hardware constraints.
arXiv:2606. 14824v1 Announce Type: cross Abstract: This document proposes a novel approach to hardware-aware neural architecture search (HW NAS) that considers the resources available on the computing platform running it, enabling its execution on various embedded devices.
arXiv:2608.21646v1 Announce Type: cross Abstract: TinyML systems are enabling machine learning (ML) inference at the edge. However, there is little quantitative analysis of such systems. This paper p...
arXiv:2603. 15106v2 Announce Type: replace Abstract: Enabling efficient deep neural network (DNN) inference on edge devices with different hardware constraints is a challenging task that typically requires DNN architectures to be specialized for each device separately.
The paper presents a novel multi‑exit computational scheme for TinyML on an ultra‑low‑power GAP9 SoC, adding confidence‑based gating points to a MobileNetV2 CNN for ImageNet‑100. By allowing inference to stop early, the approach cuts average MAC operations by 41 % (from 313 MMAC to 185 MMAC), reduces inference time by 29 % (49 ms to 35 ms), and saves 24 % in energy (2.1 mJ to 1.6 mJ per frame) with only a ~1 % drop in accuracy. Compared to a state‑of‑the‑art adaptive CNN on the same hardware, the method more than doubles computational efficiency, raising MAC/cycle from 8.1 to 17.2.
GaLe is a memory‑efficient technique that allows pretrained neural networks to run on resource‑constrained devices without retraining. It splits feature maps into a local exact component that keeps fine details and a global approximate component that preserves long‑range dependencies, enabling global operations and attention mechanisms typical of hybrid CNN‑transformer models. On ImageNet, GaLe matches exact‑inference accuracy while delivering up to 65% speedup and 90% RAM reduction on a Cortex‑M33, and it works across classification, detection, and generation tasks.
Deep Microcompression (DMC) is a hardware‑aware pipeline that combines structured pruning, quantization‑aware training, and fixed‑length bit‑packing to enable deep learning inference on bare‑metal microcontrollers. The method achieves a 55.8× weight compression on LeNet‑5 while maintaining 98.77% accuracy, and produces a dependency‑free C library with deterministic latency. On the RP2040 Cortex‑M0+ microcontroller, DMC cuts binary size threefold compared to TensorFlow Lite while matching its accuracy, and it is the first documented deployment of a standard CNN on the 2 KB SRAM ATmega328P.
arXiv:2606. 10294v1 Announce Type: cross Abstract: Deploying neural networks on unconventional hardware demands architectures that co-optimize task accuracy and platform-specific constraints such as energy cost, physical non-idealities, and numerical precision.
arXiv:2311. 17815v3 Announce Type: replace-cross Abstract: Given their increasing size and complexity, the need for efficient execution of deep neural networks has become increasingly pressing in the design of heterogeneous High-Performance Computing (HPC) and edge platforms, leading to a wide variety of proposals for specialized deep learning architectures and hardware accelerators.
arXiv:2505. 03303v4 Announce Type: replace-cross Abstract: Lightweight convolutional neural networks are often compared using results obtained with different training recipes, input settings, and pretrained checkpoints.
ENAS is a hardware‑aware neural architecture search framework tailored for TinyML on microcontrollers. It uses a static feasibility check, a cell‑based search space with various block types and skip connections, and a three‑stage hybrid search strategy (random → top‑K → mutation) with cross‑run caching. The framework runs efficiently without GPUs, achieving significant search‑time speedups and competitive accuracy on Visual Wake Words and Melanoma Cancer benchmarks across a range of microcontrollers.
arXiv:2512.04705v3 Announce Type: replace-cross Abstract: The deployment of Early-Exiting Neural Networks (EENNs) on edge accelerators requires optimizing not only the network architecture but also i...
The paper introduces a holistic framework that jointly optimizes architecture, token, and bit-width for Vision Transformers (ViTs). It uses Neural Architecture Search (AutoFormer) to find compact backbones, token merging (ToMe) to reduce information processing, and fp16 mixed‑precision inference to accelerate operations. Experiments on ImageNet‑1K and a real‑world 3D X‑ray semiconductor defect dataset show over 10× improvements in throughput and reductions in parameters, FLOPs, and energy while preserving accuracy.