arXiv AI
TicTacBench: Benchmarking Timing Closure Capabilities of Coding Agents
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arXiv AI
Jul 21
CLOSER-Bench: Evaluating Budgeted Cross-Stage Design Closure for Hardware Agents
arXiv:2607. 16632v1 Announce Type: cross Abstract: Hardware engineering exposes coding agents to a form of long-horizon work that is difficult to capture with pass-at-k: progress is continuous, tool feedback is delayed and heterogeneous, and a backend failure may require revising RTL rather than tuning another physical-design parameter.
arXiv AI
Jun 9
RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Models
arXiv:2606. 08976v1 Announce Type: new Abstract: LLM-based RTL generation and reasoning is a promising direction for hardware design automation.
arXiv AI
Jun 10
EstRTL: Functional Estimation Guided RTL Code Generation
arXiv:2606. 09867v1 Announce Type: cross Abstract: Optimizing register transfer level (RTL) code is of vital importance in hardware design.
arXiv AI
Jul 21
Can AI Agents Really Complete RTL-to-GDS? Lessons from Benchmarking Tool-Interactive EDA Workflows
arXiv:2607. 17528v1 Announce Type: new Abstract: LLM-driven agent systems have emerged as a promising paradigm for electronic design automation (EDA), demonstrating strong potential for automating complex design workflows.
arXiv Machine Learning
Jul 28
Benchmarking LLMs for Verilog Design Flows
arXiv:2607. 22759v1 Announce Type: cross Abstract: Large language models (LLMs) show promise in code generation, but their capabilities to produce correct, synthesizable hardware description language (HDL) code still remain to be properly benchmarked.
arXiv Machine Learning
Jun 5
CASS-RTL: Correctness-Aware Subspace Steering for RTL Generation with LLMs
arXiv:2606. 05680v1 Announce Type: cross Abstract: Recent advances in large language models (LLMs) have enabled the automatic synthesis (generation) of register-transfer level (RTL) code from natural language instructions, offering a promising pathway to accelerate chip design.