arXiv AI
Jun 16
LLM4RTL: Tool-Assisted LLM for RTL Generation
arXiv:2606. 15500v1 Announce Type: cross Abstract: Large language models (LLMs) have facilitated impressive progress in software engineering, code generation, tooling, and systems.
EstRTL: Functional Estimation Guided RTL Code Generation
arXiv:2606. 09867v1 Announce Type: cross Abstract: Optimizing register transfer level (RTL) code is of vital importance in hardware design.
Related stories
arXiv Machine Learning
Jul 28
Benchmarking LLMs for Verilog Design Flows
arXiv:2607. 22759v1 Announce Type: cross Abstract: Large language models (LLMs) show promise in code generation, but their capabilities to produce correct, synthesizable hardware description language (HDL) code still remain to be properly benchmarked.
arXiv Machine Learning
Jun 5
CASS-RTL: Correctness-Aware Subspace Steering for RTL Generation with LLMs
arXiv:2606. 05680v1 Announce Type: cross Abstract: Recent advances in large language models (LLMs) have enabled the automatic synthesis (generation) of register-transfer level (RTL) code from natural language instructions, offering a promising pathway to accelerate chip design.
arXiv AI
Jun 9
RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Models
arXiv:2606. 08976v1 Announce Type: new Abstract: LLM-based RTL generation and reasoning is a promising direction for hardware design automation.
arXiv AI
Aug 3
Agentic Harness for Real-World Compilers
arXiv:2603. 20075v2 Announce Type: replace-cross Abstract: Compilers are critical to modern computing, yet fixing compiler bugs is difficult.
arXiv AI
Jun 4
HighTide: An Agent-Curated Open-Source VLSI Benchmark Suite
arXiv:2606. 04126v1 Announce Type: cross Abstract: We introduce HighTide, an evolving AI-assisted benchmark suite.
arXiv AI
5d ago
CangjieBench: Benchmarking LLMs on a Low-Resource General-Purpose Programming Language
arXiv:2603. 14501v2 Announce Type: replace-cross Abstract: Large Language Models excel in high-resource programming languages but struggle with low-resource ones.
arXiv AI
Jun 15
VHDLSuite: Unified Pipeline for LLM VHDL Generation with Data Synthesis and Evaluation
arXiv:2606. 13735v1 Announce Type: cross Abstract: Large Language Models (LLM) have shown impressive capabilities in Register Transfer Level (RTL) code generation, particularly for Verilog.
arXiv AI
Jun 19
AutoPass: Evidence-Guided LLM Agents for Compiler Performance Tuning
arXiv:2606. 20373v1 Announce Type: cross Abstract: Large Language Models (LLMs) show promise for code compilation tasks, but applying them to runtime performance tuning is difficult due to complex microarchitectural effects and noisy runtime measurements.
arXiv AI
Jul 3
Understanding Agent-Based Patching of Compiler Missed Optimizations
arXiv:2607. 02370v1 Announce Type: cross Abstract: Compiler missed optimizations refer to cases in which compilers failed to optimize certain code.
arXiv AI
Jul 21
CLOSER-Bench: Evaluating Budgeted Cross-Stage Design Closure for Hardware Agents
arXiv:2607. 16632v1 Announce Type: cross Abstract: Hardware engineering exposes coding agents to a form of long-horizon work that is difficult to capture with pass-at-k: progress is continuous, tool feedback is delayed and heterogeneous, and a backend failure may require revising RTL rather than tuning another physical-design parameter.
arXiv AI
Jul 28
CodeEvo: Interaction-Driven Synthesis of Code-centric Data through Hybrid and Iterative Feedback
arXiv:2507. 22080v2 Announce Type: replace-cross Abstract: Acquiring high-quality instruction-code pairs is essential for training Large Language Models for code generation.