arXiv:2607. 20019v1 Announce Type: new Abstract: Design rule check (DRC) closure remains a major bottleneck in advanced-node physical design.
By Bing-Yue Wu, Chia-Tung Ho, Haoyu Yang, Brucek Khailany, Vidya A. Chhabria
arXiv:2607. 12605v1 Announce Type: cross Abstract: Large language models (LLMs) have improved automated program repair (APR), but two limitations remain.
By Zhili Huang, Ling Xu, Hongyu Zhang
arXiv:2605. 06936v3 Announce Type: replace-cross Abstract: LLM-based agents are increasingly applied to the "last mile" of Electronic Design Automation (EDA): repairing residual sign-off Design Rule Check (DRC) violations and converging Power-Performance-Area (PPA) targets after tool runs.
By Pengju Liu, Nuo Xu, Jinwei Tang, Yu Cao, Caiwen Ding
AgenticCADedit introduces a stateful, tool‑mediated approach to multimodal 3D CAD editing, transforming the process from generating a single complete program to executing a sequence of incremental, verifiable actions on a persistent CAD state. By committing each step, inspecting geometry, and selectively reverting faulty operations, the method preserves partial progress and builds upon earlier edits. Experiments across three large language models show substantial gains in validity and acceptance, with the weakest baseline model’s validity rising from 51.0% to 94.8% and a token‑cost reduction of 66.7% compared to neuralCAD‑Edit.
By Saptarshi Neil Sinha, Mika Silvan Goschke, Paul Julius K\"uhn, Arjan Kuijper, Michael Weinmann
The paper introduces a dictionary-guided HDL repair system that uses ANTLR-derived mutation vocabularies and a simulation-divergence fault localization module to generate syntactically valid Verilog mutations. The mutation operator performs token substitutions, insertions, and deletions via regex matching, while the fault localization scores source lines based on proximity to diverging output wires, guiding the search. Evaluated on the CirFix benchmark, the approach achieves correct repairs on 14 bug variants, including a multi-bug case, and outperforms CirFix with an 18x speedup on a two-edit benchmark.
By Maisha Mastora, Dean Sullivan
arXiv:2606. 05680v1 Announce Type: cross Abstract: Recent advances in large language models (LLMs) have enabled the automatic synthesis (generation) of register-transfer level (RTL) code from natural language instructions, offering a promising pathway to accelerate chip design.
By Mohammad Akyash, Nowfel Mashnoor, Kimia Azar, Hadi Kamali