arXiv AI September 12, 2026 By Elia Mateu-Barriendos, \'Alvaro G\'omez-Pau, Josep Rius, Daniel Arum\'i, Rosa Rodr\'iguez-Monta\~n\'es, Salvador Manich

A Time-Based Readout for Vector-Matrix Multiplication in Fully Analog Memristive SNNs

Read the original on arXiv AI →

The paper introduces a fully analog readout architecture for vector-matrix multiplication in spiking neural networks that uses voltage-to-time conversion instead of conventional current-mode circuits. By sensing the column voltage directly, the design eliminates the need for current summing and scaling circuitry, thereby reducing area and power consumption. Post-layout simulations of a 10×1 SNN in 130 nm CMOS and tests on a 64×10 digit‑classification network demonstrate the feasibility and efficiency of the proposed approach.

Machine-generated by The Flow from the publisher's headline and feed description — not written or checked by a human. The full article lives at arXiv AI.

Hugging Face Trending Papers

Jun 11

Modern analog computing for solving differential and matrix equations

In recent years, driven by the computational demands of data-intensive applications such as artificial intelligence and scientific computing, analog computing has gained renewed interest. Given the diversity of computational tasks and recent advancements in analog CMOS circuits and resistive memory technologies, we refer to the evolving landscape as modern analog computing.

arXiv AI

Jun 12

Modern analog computing for solving differential and matrix equations

arXiv:2606. 13179v1 Announce Type: cross Abstract: In recent years, driven by the computational demands of data-intensive applications such as artificial intelligence and scientific computing, analog computing has gained renewed interest.

By Zhong Sun, Piergiulio Mannocci, Manuel Le Gallo, Abu Sebastian

arXiv AI

Jul 17

Multibit neural inference in a N-ary crossbar architecture

arXiv:2604. 26979v2 Announce Type: replace-cross Abstract: In-memory computing (IMC) is a paradigm that enables neural network inference by computing analog matrix-vector multiplications (MVM) directly in memory crossbar arrays, with the potential for energy efficiency gains over conventional von Neumann architectures.

By Anatole Moureaux, Anthony Lopes Temporao, Flavio Abreu Araujo

efficiency

arXiv AI

Jun 3

CRAM-ER: Error-Resilient Spintronic Computational Random Access Memory for Scalable In-Memory Computation

arXiv:2606. 02781v1 Announce Type: cross Abstract: Deep neural networks (DNNs) have achieved state-of-the-art performance across diverse domains.

By Sohan Salahuddin Mugdho, Md. Shahedul Hasan, Brahmdutta Dixit, Yang Lv, Jian-Ping Wang, Cheng Wang

fine-tuning efficiency benchmarks

arXiv AI

Sep 1

ITP-STDP: A Hardware-Efficient Intrinsic-Timing Power-of-Two Synaptic Learning Engine for On-Chip SNNs

arXiv:2606.06159v2 Announce Type: replace-cross Abstract: Spiking neural networks (SNNs) have the potential to emerge as the third generation of neural networks and have attracted increasing attentio...

By Haihang Xia, Xinyu Zhao, Xuecheng Wang, John Goodenough, Charith Abhayaratne, Panagiotis A. Panagiotou, Chunyi Song, Tiantai Deng

benchmarks

arXiv AI

Jun 6

ITP-STDP: An Intrinsic-Timing Power-of-Two Learning Engine for On-Chip SNN Training

arXiv:2606. 06159v1 Announce Type: cross Abstract: Spiking neural networks (SNNs) have the potential to emerge as the third generation of neural networks and have attracted increasing attention across a wide range of applications.

By Haihang Xia, Xinyu Zhao, Xuecheng Wang, John Goodenough, Charith Abhayaratne, Panagiotis A. Panagiotou, Chunyi Song, Tiantai Deng

benchmarks

One email a morning, machine-written

Related stories

Modern analog computing for solving differential and matrix equations

Modern analog computing for solving differential and matrix equations

Multibit neural inference in a N-ary crossbar architecture

CRAM-ER: Error-Resilient Spintronic Computational Random Access Memory for Scalable In-Memory Computation

ITP-STDP: A Hardware-Efficient Intrinsic-Timing Power-of-Two Synaptic Learning Engine for On-Chip SNNs

ITP-STDP: An Intrinsic-Timing Power-of-Two Learning Engine for On-Chip SNN Training