The paper introduces a toolchain that enables machine‑learning model development on AWS EC2 F2 cloud FPGAs using high‑level Vitis HLS. It implements a complete Vitis HLS to HDK bridge to AFI workflow, a four‑level methodology (FP32 PyTorch, bit‑accurate quantized Python, HLS C‑simulation, physical FPGA) for error localization, and documents deployment, timing closure, and HLS engineering decisions. The authors validate the approach by implementing TinyBERT’s embedding layer and first encoder layer on FPGA, noting that weight streaming from host DRAM results in poor performance compared to CPU/GPU implementations.
arXiv:2602. 15751v2 Announce Type: replace-cross Abstract: This paper presents an end-to-end demonstration of a viable, ultra-fast, radiation-hard machine learning (ML) application on FPGAs, which could be used in future high-energy physics experiments.
Application-specific FPGA accelerators offer substantial performance and energy-efficiency gains across many application domains, but developing them is costly, often requiring months of specialized effort. Even with high-level synthesis (HLS), designers still need extensive hardware expertise to build high-performance accelerators.
Large Language Model agents are being explored for chip design, but most methods work directly at RTL. This study compares Direct RTL Design, Agent-based HLS Design, Post-Compiler HLS Refinement, and Post-HLS RTL Refinement, and proposes a combined workflow called Agent-based HLS with RTL Refinement (AHRR). Using FPGAs for evaluation, AHRR achieves a 2.6× geometric‑mean speedup over Direct RTL Design across an 11‑task benchmark suite, demonstrating that higher‑level abstractions and subsequent RTL refinement can improve chip design efficiency.
The paper introduces VHDLBench, a benchmark and fine‑tuning framework for large language models (LLMs) applied to VHDL-based chip design. It presents a dataset of over 18,500 syntax‑verified VHDL examples, fine‑tunes five 7B‑parameter LLMs with QLoRA, and evaluates them through a three‑level pipeline—syntax/synthesis validation, functional simulation, and FPGA prototyping on Zynq SoCs. Results show up to 92% syntax correctness and 73% functional accuracy, with DeepSeek‑Coder achieving the best performance and successful deployment on real hardware.
arXiv:2608. 06791v1 Announce Type: cross Abstract: Application-specific FPGA accelerators offer substantial performance and energy-efficiency gains across many application domains, but developing them is costly, often requiring months of specialized effort.
QiMeng-ChipV-RTL is a multi‑agent framework that tackles the challenges of generating Register‑Transfer Level (RTL) code for industrial IP‑level hardware design. By partitioning long design documents into short, localized tasks and using hierarchical planning, localized code generation, interface‑consistent merging, and AST‑guided debugging, it scales to complex specifications. Experiments on the RealBench benchmark show ChipV-RTL achieves a 45.0% pass rate, outperforming state‑of‑the‑art LLMs and agents which reach only 21.6%.
arXiv:2607. 03652v1 Announce Type: cross Abstract: Transformer blocks are prevalent in large language model (LLM) but present deployment challenges due to their challenging computational and memory demands.
arXiv:2605. 16138v2 Announce Type: replace Abstract: Neural architecture search (NAS) is a powerful approach for automating model design, but existing methods often optimize for accuracy alone or rely on proxy metrics such as bit operations (BOPs) that correlate poorly with hardware cost.
arXiv:2606. 13735v1 Announce Type: cross Abstract: Large Language Models (LLM) have shown impressive capabilities in Register Transfer Level (RTL) code generation, particularly for Verilog.
arXiv:2606. 10008v1 Announce Type: cross Abstract: Spiking Neural Networks (SNNs) provide a naturally temporal machine-learning framework.
The paper introduces a development environment where large language model (LLM) agents design RISC‑V CPUs that are implemented on an FPGA for real‑time performance evaluation. Using on‑board measurements, the approach guides design decisions and accelerates evaluation, achieving a 9.6× speedup over single‑threaded RTL simulation. In a case study, FPGA measurements uncovered long‑run performance degradation that short diagnostic runs missed, leading to candidate selection, root‑cause analysis, and a fix.
The article reviews the growing use of Large Language Models (LLMs) for generating Verilog code, a key hardware description language in electronic design automation. It surveys 102 papers, covering conferences, journals, and preprints, and addresses four research questions about LLM selection, datasets, techniques, and alignment strategies. The review identifies current limitations and proposes a roadmap for future research in LLM-assisted hardware design.