arXiv AI By Leo Itoh, Junichiro Kadomoto

LLM Agent-Based Design of RISC-V CPUs with FPGA-in-the-Loop Evaluation

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The paper introduces a development environment where large language model (LLM) agents design RISC‑V CPUs that are implemented on an FPGA for real‑time performance evaluation. Using on‑board measurements, the approach guides design decisions and accelerates evaluation, achieving a 9.6× speedup over single‑threaded RTL simulation. In a case study, FPGA measurements uncovered long‑run performance degradation that short diagnostic runs missed, leading to candidate selection, root‑cause analysis, and a fix.

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