Towards Data Science

SPP-Net Paper Walkthrough: Breaking the Fixed-Size Constraint

Learn how Spatial Pyramid Pooling enables CNNs to handle any image size, with a from-scratch PyTorch implementation The post SPP-Net Paper Walkthrough: Breaking the Fixed-Size Constraint appeared first on Towards Data Science .

Towards Data Science
Sep 23

I Trained a Tiny Network to Compress Data. It Drew a Pentagon.

The article describes how the author replicated Anthropic’s “Toy Models of Superposition” using only NumPy, hand‑derived gradients, and no external libraries. By training a very small neural network to compress data, the model produced a pentagon shape as its output. The post showcases a minimal, from‑scratch implementation of a complex concept in machine learning.

By Utkarsh Mangal
arXiv AI
Jun 16

An affordable hardware-aware neural architecture search for deploying convolutional neural networks on ultra-low-power computing platforms

arXiv:2606. 16290v1 Announce Type: cross Abstract: Hardware-aware neural architecture search (HW-NAS) allows the integration of Convolutional Neural Networks (CNNs) in microcontrollers devices by automatically designing neural architectures that can fit prearranged hardware constraints.

By Andrea Mattia Garavagno, Edoardo Ragusa, Antonio Frisoli, Paolo Gastaldo
arXiv Computer Vision
2d ago

Right In-Place (RiP) Convolution: A Simple, General, and Near-Optimal Strategy for Memory-Efficient CNN Inference

The paper introduces Right In-Place (RiP) convolution, a memory‑efficient strategy that corrects and generalizes previous in‑place convolution formulations to arbitrary stride, dilation, padding, and rectangular kernels. RiP aligns each layer’s input and output within a shared workspace, enabling safe, row‑major access with minimal memory overhead. Experiments on 10,000 random layers and 84 layers from 25 architectures show no corruption, matching or improving on existing herringbone workspaces while reducing memory usage by up to 24.8% and lowering peak activation memory on Raspberry Pi Pico MCUs by 12.5–33.3% without affecting cycle counts.

By Opegbemi Matthias Busoye, Tolulope Matthew Busoye, Eghonghon-aye Eigbe
arXiv Machine Learning
Jun 2

Scaling Parallel Sequence Models to Foundation-Scale Vision Encoders

arXiv:2606. 00746v1 Announce Type: cross Abstract: Vision foundation models are bottlenecked by the quadratic cost of self-attention, which limits usable resolution and increases the cost of large-scale pretraining.

By Yitong Jiang, Hongjun Wang, Collin McCarthy, Hanrong Ye, David Wehr, Xinhao Li, Qi Dou, Tianfan Xue, Ka Chun Cheung, Simon See, Wonmin Byeon, Ke Chen, Kai Han, Jinwei Gu, Hongxu Yin, Pavlo Molchanov, Jan Kautz, Sifei Liu