arXiv:2606. 14824v1 Announce Type: cross Abstract: This document proposes a novel approach to hardware-aware neural architecture search (HW NAS) that considers the resources available on the computing platform running it, enabling its execution on various embedded devices.
By Andrea Mattia Garavagno, Edoardo Ragusa, Paolo Gastaldo, Antonio Frisoli
arXiv:2608.21646v1 Announce Type: cross
Abstract: TinyML systems are enabling machine learning (ML) inference at the edge. However, there is little quantitative analysis of such systems. This paper p...
By Yujie Zhang, Dhananjaya Wijerathne, Zhaoying Li, Tulika Mitra
arXiv:2603. 15106v2 Announce Type: replace Abstract: Enabling efficient deep neural network (DNN) inference on edge devices with different hardware constraints is a challenging task that typically requires DNN architectures to be specialized for each device separately.
By Mark Deutel, Simon Geis, Axel Plinge
The paper presents a novel multi‑exit computational scheme for TinyML on an ultra‑low‑power GAP9 SoC, adding confidence‑based gating points to a MobileNetV2 CNN for ImageNet‑100. By allowing inference to stop early, the approach cuts average MAC operations by 41 % (from 313 MMAC to 185 MMAC), reduces inference time by 29 % (49 ms to 35 ms), and saves 24 % in energy (2.1 mJ to 1.6 mJ per frame) with only a ~1 % drop in accuracy. Compared to a state‑of‑the‑art adaptive CNN on the same hardware, the method more than doubles computational efficiency, raising MAC/cycle from 8.1 to 17.2.
By Luca Crupi, Lorenzo Lamberti, Alessandro Giusti, Daniele Palossi
GaLe is a memory‑efficient technique that allows pretrained neural networks to run on resource‑constrained devices without retraining. It splits feature maps into a local exact component that keeps fine details and a global approximate component that preserves long‑range dependencies, enabling global operations and attention mechanisms typical of hybrid CNN‑transformer models. On ImageNet, GaLe matches exact‑inference accuracy while delivering up to 65% speedup and 90% RAM reduction on a Cortex‑M33, and it works across classification, detection, and generation tasks.
By Alberto Ancilotto, Elisabetta Farella
Deep Microcompression (DMC) is a hardware‑aware pipeline that combines structured pruning, quantization‑aware training, and fixed‑length bit‑packing to enable deep learning inference on bare‑metal microcontrollers. The method achieves a 55.8× weight compression on LeNet‑5 while maintaining 98.77% accuracy, and produces a dependency‑free C library with deterministic latency. On the RP2040 Cortex‑M0+ microcontroller, DMC cuts binary size threefold compared to TensorFlow Lite while matching its accuracy, and it is the first documented deployment of a standard CNN on the 2 KB SRAM ATmega328P.
By Opegbemi Matthias Busoye, Tolulope Matthew Busoye, Eghonghon-aye Eigbe