arXiv AI

Hardware Design and Security in the Era of Chiplets and LLMs

arXiv:2608. 05063v1 Announce Type: cross Abstract: The semiconductor industry is undergoing a dual revolution: the shift toward heterogeneous 2.

arXiv AI
Sep 12

Architecting the Secure AI-SOC: A Neurosymbolic Framework for Pipeline Integrity and Threat Mitigation

The paper proposes a neurosymbolic defense architecture for AI-enhanced Security Operations Centers (AI‑SOCs) that protects against indirect prompt injection via log poisoning. It combines deterministic SIEM decoders as a pre‑filter with NeMo Guardrails for semantic validation, and adds a closed‑loop telemetry system for Human‑in‑the‑Loop visibility. Experimental results mapped to the MITRE ATLAS taxonomy show the approach effectively dismantles promptware kill chains and delivers a resilient, observable defense for next‑generation AI‑SOCs.

By Anna Gazani, Spyridon Kounoupidis, Panagiotis Katsaros, Nikolaos Kekatos, Grigorios Tsoumakas, Georgios Koutidis
arXiv AI
Sep 10

Hardware Trojan Threats to Multi-Chiplet Photonic Neural Network Accelerators

The paper discusses hardware Trojan threats to Multi-Chiplet Photonic Neural Network Accelerators (MCPNAs), which combine photonic computation, communication, and heterogeneous chiplet integration for scalable, energy‑efficient AI acceleration. It highlights that the distributed architecture and use of third‑party chiplets create significant hardware security risks. The study examines these threats across confidentiality, integrity, and availability dimensions.

By Sudeep Pasricha