arXiv AI
Aug 6
Hardware Design and Security in the Era of Chiplets and LLMs
arXiv:2608. 05063v1 Announce Type: cross Abstract: The semiconductor industry is undergoing a dual revolution: the shift toward heterogeneous 2.
LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges
arXiv:2605. 10807v4 Announce Type: replace-cross Abstract: The integration of Large Language Models (LLMs) into Electronic Design Automation (EDA) and hardware security is rapidly reshaping the semiconductor industry.
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arXiv Machine Learning
Jun 16
Data-Centric Benchmarking of Exploit Generation in LLMs: Understanding the Impact of Fine-Tuning
arXiv:2606. 15123v1 Announce Type: cross Abstract: We study the task of CVE-conditioned exploit generation, where a model drafts proof-of-concept (PoC) exploits given software vulnerability context.
arXiv AI
Jun 19
Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement
arXiv:2606. 19387v1 Announce Type: cross Abstract: Large language models (LLMs) have achieved remarkable success in software development.
arXiv AI
Jul 28
Poster: Rethinking Security in LLM Code Generation through Real-World Risk Scenarios
arXiv:2607. 23088v1 Announce Type: cross Abstract: Large Language Models (LLMs) are widely used for code generation, yet their security behavior in realistic development workflows remains underexplored.
arXiv AI
Aug 11
LAUDE: LLM-Assisted Unit Test Generation and Debugging of Hardware DEsigns
arXiv:2601. 08856v3 Announce Type: replace-cross Abstract: Unit tests are critical in the hardware design lifecycle to ensure that component design modules are functionally correct and conform to the specification before they are integrated at the system level.
arXiv AI
Jun 4
TamperBench: Systematically Stress-Testing LLM Safety Under Fine-Tuning and Tampering
arXiv:2602. 06911v2 Announce Type: replace-cross Abstract: As increasingly capable open-weight large language models (LLMs) are deployed, improving their tamper resistance against unsafe modifications, whether accidental or intentional, becomes critical to minimize risks.
arXiv AI
Jun 15
VHDLSuite: Unified Pipeline for LLM VHDL Generation with Data Synthesis and Evaluation
arXiv:2606. 13735v1 Announce Type: cross Abstract: Large Language Models (LLM) have shown impressive capabilities in Register Transfer Level (RTL) code generation, particularly for Verilog.
arXiv AI
Aug 12
Generating Attacks for LLMs with GFlowNets
arXiv:2608. 10171v1 Announce Type: new Abstract: The rapid advancement of Large Language Models (LLMs) has facilitated their ubiquitous integration into various domains, leading to widespread adoption.
arXiv AI
Aug 5
AgenticSCR: An Autonomous Agentic Secure Code Review for Immature Vulnerabilities Detection
arXiv:2601. 19138v2 Announce Type: replace-cross Abstract: Secure code review is critical during pre-integration, where Atlassian developers rely on lightweight analysis tools, while deep security assessment is deferred to later stages, delaying feedback and increasing remediation costs.
arXiv AI
Jul 3
RedCoder: Automated Multi-Turn Red Teaming for Code LLMs
arXiv:2507. 22063v2 Announce Type: replace-cross Abstract: Large Language Models (LLMs) for code generation (i.
arXiv AI
Jun 24
RIFT-Bench: Dynamic Red-teaming For Agentic AI Systems
arXiv:2606. 23927v1 Announce Type: new Abstract: Agentic AI systems powered by large language models (LLMs) are rapidly evolving into autonomous decision-making systems, exposing attack vectors beyond those of traditional LLM vulnerabilities.
arXiv AI
Jul 14
DeepBias: Adaptive In-depth Probing of Social Biases in LVLMs
arXiv:2607. 11228v1 Announce Type: cross Abstract: While Large Vision-Language Models (LVLMs) demonstrate remarkable capabilities, they remain highly susceptible to embedded social biases.