arXiv Machine Learning

Hardware-Aware Deployment of Joint SAR Compression and Despeckling on FPGA

arXiv:2608. 11271v1 Announce Type: cross Abstract: Next-generation Synthetic Aperture Radar (SAR) missions will generate data far faster than they can downlink, making onboard data reduction essential for near-real-time Earth observation.

arXiv Machine Learning
Jul 1

FlexViT: A Flexible FPGA-based Accelerator for Edge Vision Transformers

arXiv:2606. 31938v1 Announce Type: cross Abstract: Deploying Vision Transformer (ViT) models on edge platforms remains challenging due to their high computational demands and the architectural heterogeneity of modern hybrid ViT models, which incorporate both fully connected and convolutional layers.

By Hubert Dymarkowski, Xingjian Fu, Rappy Saha, Jude Haris, Jos\'e Cano
arXiv Computer Vision
Aug 31

Memory-efficient GPU pipelines for real-time non-line-of-sight reconstruction

The paper presents memory‑efficient GPU pipelines that accelerate real‑time non‑line‑of‑sight (NLOS) reconstruction. By redesigning two wave‑based algorithms—f‑k migration and phasor‑fields—with fused kernels, warp‑level photon binning, batched transforms, CUDA graph replay, and selective FP16 storage, the authors achieve up to 42× speed‑ups over a reference streaming pipeline and 14× over the fastest published GPU baseline while reducing memory usage to as little as 2.5%. The work also includes an ablation study of implementation choices and introduces three denoising strategies that leverage the increased frame budget for future NLOS video processing.

By Alfonso L\'opez-Ruiz, Diego Royo
Hugging Face Trending Papers
Aug 12

HAMP-LIC: Hessian-Aware Mixed-Precision Post-Training Quantization for Learned Image Compression

Use this plain-text version for the arXiv abstract field: Learned image compression (LIC) models achieve strong rate-distortion performance but are hindered by high computational complexity and encoding-decoding mismatches across heterogeneous hardware platforms. Uniform fixed-precision quantization alleviates these issues but suffers severe quality degradation at low bit widths because it ignores differences in the quantization sensitivities of individual layers.

arXiv Machine Learning
Sep 17

FAME: An FPGA-Based Platform for Approximate Multipliers Evaluation with Pattern-Guided DNN Retraining

FAME is an FPGA-based platform that evaluates approximate multipliers directly in hardware, eliminating slow CPU/GPU LUT emulation and reducing evaluation time for DNN inference. It also introduces a pattern-guided retraining method that uses multiplier-specific patterns to recover accuracy losses. Experiments on ResNet‑18 and MobileNetV2 over ImageNet show up to 3.47× faster multiplier evaluation and a 65.5% accuracy improvement over prior retraining approaches.

By Rappy Saha, Nima Amirafshar, Jude Haris, Nima Taherinejad, Jos\'e Cano
Hugging Face Trending Papers
Jun 24

Energy-Efficient CNN Acceleration with MSDF Digit-Serial Arithmetic on FPGA

This paper presents an energy-efficient hardware acceleration of the convolutional layers in the U-Net architecture for image segmentation, implemented on FPGA. While digit-serial arithmetic, particularly most-significant-digit-first (MSDF) techniques, offers a compact hardware footprint, it suffers from initial latency before producing the first output digit.

arXiv Machine Learning
Aug 3

Enabling Low-Latency Machine learning on Radiation-Hard FPGAs with hls4ml

arXiv:2602. 15751v2 Announce Type: replace-cross Abstract: This paper presents an end-to-end demonstration of a viable, ultra-fast, radiation-hard machine learning (ML) application on FPGAs, which could be used in future high-energy physics experiments.

By Katya Govorkova, Julian Garcia Pardinas, Vladimir Loncar, Victoria Nguyen, Sebastian Schmitt, Marco Pizzichemi, Loris Martinazzoli, Eluned Anne Smith