arXiv AI
Learning to Formulate: Agentic Hardware-Software Co-Design of AI Infrastructure through Progressive Optimization and Verification
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Ave: Guiding Agentic GPU Optimization Using Data-Flow Invariants
arXiv:2604.18616v2 Announce Type: replace-cross Abstract: LLM coding agents can generate correct GPU kernels, but their performance still trails expert libraries. Reaching peak throughput requires co...
arXiv Machine Learning
Jun 25
ASAP: Agent-System Co-Design for Wall-Clock-Centered Auto HPO Research for ML Experiments
arXiv:2606. 25207v1 Announce Type: new Abstract: Hyperparameter Optimization (HPO) is essential for maximizing machine learning model performance, and its core challenge is sample efficiency: finding strong configurations within a limited budget.
arXiv AI
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Agentic Architect: An Agentic AI Framework for Architecture Design Exploration and Optimization
Agentic Architect is a new framework that uses large language models to automatically evolve and optimize CPU microarchitectural designs. Starting from a seed design, the LLM proposes code changes, which are compiled, simulated, and evaluated against performance, area, and power constraints, with results feeding back into subsequent iterations. The framework was tested on prefetching, cache replacement, and branch prediction, achieving notable speedups and area reductions compared to state‑of‑the‑art designs.
arXiv AI
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Agentic Design Space Exploration for Joint Hardware Configuration Selection and Mapping of AI Inference Workloads on Heterogeneous Edge SoCs
The paper introduces TraceDSE, an agentic design space exploration framework for jointly mapping AI inference workloads to heterogeneous edge SoCs and configuring each processing unit. Unlike traditional black-box optimization, TraceDSE uses a proposer‑critic loop powered by large language models and enriched with system execution traces to identify bottlenecks and refine design choices. Experiments on an Intel Meteor Lake SoC show that TraceDSE outperforms state‑of‑the‑art evolutionary and Bayesian methods, improving Pareto frontier hypervolume by up to 68% while reducing hardware evaluations by 6–9×.
arXiv AI
Sep 21
Can Agents Design Better Chips with a Higher Level Abstraction?
Large Language Model agents are being explored for chip design, but most methods work directly at RTL. This study compares Direct RTL Design, Agent-based HLS Design, Post-Compiler HLS Refinement, and Post-HLS RTL Refinement, and proposes a combined workflow called Agent-based HLS with RTL Refinement (AHRR). Using FPGAs for evaluation, AHRR achieves a 2.6× geometric‑mean speedup over Direct RTL Design across an 11‑task benchmark suite, demonstrating that higher‑level abstractions and subsequent RTL refinement can improve chip design efficiency.
arXiv AI
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Do AI Agents Understand Computer Architecture?
The paper investigates whether AI agents truly understand computer architecture by comparing their performance when the same 15‑dimensional accelerator design space is presented either as meaningful architectural knobs or as anonymous variables. Using the AutoTuring framework, the authors find that agents with architectural knowledge outperform blind agents on a nine‑kernel FP16 GEMM benchmark, yet a critic loop can largely recover this advantage. The study highlights that architectural knowledge and structured critique act as substitutes rather than complements in improving agent performance.