Learning-Assisted Congestion-Aware Route Scheduling for Semiconductor Fab Material Control Systems
Read the original on arXiv AI →The Flow has not summarised this story yet — read it at arXiv AI.
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The paper proposes a deployment‑focused framework for deadline‑constrained network control, introducing the Effective Congestion (EC) metric family and Uniform Path Grouping (UPG) heuristic to better capture traffic urgency and balance load. It integrates these with a Multi‑Agent Deep Reinforcement Learning architecture (MADRL EC (p*)) that combines a distributed scheduler and a centralized RL router. A unified training objective merges live‑reward, pre‑collected‑reward, and policy‑imitation terms, leading to the Model‑Guided Annealed Reinforcement Learning (MGA‑RL) protocol built on DDPG, which generalizes offline‑to‑online learning for demonstration‑driven training.
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