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arXiv AI By Saeid Rajabi, Aly Moussa, Vishal Saxena, Chengmo Yang, Satwik Patnaik

AnalogPortBench: Benchmarking LLMs on Analog Circuit Porting

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AnalogPortBench is a new benchmark comprising 54 tasks that evaluate how well large language models (LLMs) can port ten analog circuits—from current mirrors to telescopic amplifiers—across process nodes, specifically from a 0.18 µm process to the SKY130 PDK. The tasks vary in difficulty, ranging from straightforward ports to reduced supply and stricter specifications, and include infeasible scenarios; each feasible task has a verified reference design at five process corners. Experiments with six leading LLMs show that while models can handle simple circuit ports, they rarely redesign headroom‑sensitive amplifiers, often miss infeasible specifications, and benefit more from simulation feedback than from additional samples or reasoning steps.

Machine-generated by The Flow from the publisher's headline and feed description — not written or checked by a human. The full article lives at arXiv AI.

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