arXiv:2605. 24033v2 Announce Type: replace Abstract: Mechanistic interpretability typically discovers circuits and then argues what they do from examples and ablations.
By Neel Somani
ChipMEM introduces a verification‑grounded memory layer for electronic design automation agents that combines cross‑task procedural memory with within‑trajectory statistical guidance. The procedural component stores a skill only after it passes synthesis, simulation, or formal checks, while a Bayesian component ranks recovery strategies based on tool‑call outcomes. Experiments on RTLRewriter‑Bench and CVDP tasks show that ChipMEM improves equivalence‑passing outputs and area metrics compared to agents without memory.
By Abdulrahman AlRabah, Joshua Mabry, Dilek Hakkani-T\"ur, Abdussalam Alawini, Hamid Shojaei, Kartik Hegde, Sandesh Adhikary
arXiv:2606. 05680v1 Announce Type: cross Abstract: Recent advances in large language models (LLMs) have enabled the automatic synthesis (generation) of register-transfer level (RTL) code from natural language instructions, offering a promising pathway to accelerate chip design.
By Mohammad Akyash, Nowfel Mashnoor, Kimia Azar, Hadi Kamali
The paper introduces EvoResearcher, a training‑free, inference‑time protocol that enables a frozen large language model to perform cost‑bounded self‑reflection and early stopping. By iterating through generate → self‑critique → revise steps until a maximum depth or a CONFIRMED sentinel is reached, the model can self‑verify its answers within a strict compute budget. The protocol incorporates four self‑reflective meta‑reward components—correctness, efficiency, reflection depth, and tool‑call diversity—implemented as prompt‑level mechanisms, and is validated on Big‑Bench Hard, GSM8K, and MATH benchmarks, achieving comparable accuracy while terminating 82‑88% of items early with only about 2.1 generations per question.
By Wei Yu, Suxing Liu, Minjie Yu, Jiahao Wang, Zhijian Zheng, Haocheng Deng, Bing Li
arXiv:2601. 12186v3 Announce Type: replace-cross Abstract: Multi-domain thinking verifiers trained via Reinforcement Learning with Verifiable Rewards (RLVR) are a cornerstone of modern post-training.
By Vatsal Venkatkrishna, Indraneil Paul, Iryna Gurevych
arXiv:2606. 18284v1 Announce Type: cross Abstract: The limiting resource for training agents via reinforcement learning (RL) is increasingly frontier task supply: valid, solvable tasks just difficult enough to train the current model.
By Lorenz Wolf, Connor Watts, Roger Creus Castanyer, Geoffrey Bradway, Maxwill Lin, Augustine N. Mavor-Parker, Matthew Daborn-Sargent