arXiv AI June 19, 2026 By Huanghaohe Zou, Peng Han, Emad Nazerian, Mafu Zhang, Zhicheng Guo, Alex Q. Huang

PCBSchemaGen: Reward-Guided LLM Code Synthesis for Printed Circuit Boards (PCB) Schematic Design with Structured Verification

arXiv:2602. 00510v2 Announce Type: replace Abstract: Most LLM code-synthesis benchmarks rely on unit tests as the reward oracle, but PCB schematic design has none: correctness is defined by structured physical constraints over real IC packages and pin-level assignments, per-task golden references are unavailable, and SPICE simulation does not validate schematic-level correctness.

Summary generated by The Flow from the publisher's feed. The full article lives at arXiv AI.

arXiv Machine Learning

Jul 30

Towards Verifiable Transformers: Solver-Checkable Circuit Explanations

arXiv:2605. 24033v2 Announce Type: replace Abstract: Mechanistic interpretability typically discovers circuits and then argues what they do from examples and ablations.

By Neel Somani

llms rag safety

arXiv Machine Learning

Jun 5

CASS-RTL: Correctness-Aware Subspace Steering for RTL Generation with LLMs

arXiv:2606. 05680v1 Announce Type: cross Abstract: Recent advances in large language models (LLMs) have enabled the automatic synthesis (generation) of register-transfer level (RTL) code from natural language instructions, offering a promising pathway to accelerate chip design.

By Mohammad Akyash, Nowfel Mashnoor, Kimia Azar, Hadi Kamali

llms rag agents fine-tuning safety

arXiv AI

Jun 3

Aletheia: What Makes RLVR For Code Verifiers Tick?

arXiv:2601. 12186v3 Announce Type: replace-cross Abstract: Multi-domain thinking verifiers trained via Reinforcement Learning with Verifiable Rewards (RLVR) are a cornerstone of modern post-training.

By Vatsal Venkatkrishna, Indraneil Paul, Iryna Gurevych

reinforcement-learning

arXiv AI

Jun 18

Breaking the Solver Bottleneck: Training Task Generators at the Learnable Frontier

arXiv:2606. 18284v1 Announce Type: cross Abstract: The limiting resource for training agents via reinforcement learning (RL) is increasingly frontier task supply: valid, solvable tasks just difficult enough to train the current model.

By Lorenz Wolf, Connor Watts, Roger Creus Castanyer, Geoffrey Bradway, Maxwill Lin, Augustine N. Mavor-Parker, Matthew Daborn-Sargent

agents reinforcement-learning

arXiv AI

Jun 9

RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Models

arXiv:2606. 08976v1 Announce Type: new Abstract: LLM-based RTL generation and reasoning is a promising direction for hardware design automation.

By Jing Wang, Shang Liu, Wenji Fang, Yuchao Wu, Yugao Zhu, Zhiyao Xie

llms benchmarks

arXiv Machine Learning

Jun 24

Not All Invariants Are Equal: Curating Training Data to Accelerate Program Verification with SLMs

arXiv:2603. 15510v2 Announce Type: replace Abstract: The synthesis of inductive loop invariants remains a critical bottleneck in automated program verification.

By Ido Pinto, Yizhak Yisrael Elboher, Haoze Wu, Nina Narodytska, Guy Katz

llms fine-tuning

Related stories

Towards Verifiable Transformers: Solver-Checkable Circuit Explanations

CASS-RTL: Correctness-Aware Subspace Steering for RTL Generation with LLMs

Aletheia: What Makes RLVR For Code Verifiers Tick?

Breaking the Solver Bottleneck: Training Task Generators at the Learnable Frontier

RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Models

Not All Invariants Are Equal: Curating Training Data to Accelerate Program Verification with SLMs