The paper introduces BLADE, a reliability‑aware method for selecting the boundary between spiking and artificial neural network components in hybrid event‑based object detectors. It jointly optimizes boundary placement and early‑exit settings for reliability, accuracy, execution time, and energy, using fault injection to guide design. Experiments show a 0.691 mAP@0.5 with 15.82 mJ energy when the ANN exits early, and that protecting a single floating‑point exponent bit eliminates catastrophic failures while a fully SNN configuration retains 96.5% reliability under severe faults.
arXiv:2607. 11914v1 Announce Type: cross Abstract: A central goal of current Spiking Neural Network (SNN) research is to improve their accuracy toward becoming low-power alternatives to Artificial Neural Networks (ANNs).
The paper introduces four new event‑based vision datasets created with the ANTShapes simulation tool, designed to support object classification research using spiking neural networks (SNNs). These datasets vary in difficulty and are benchmarked against established spiking datasets such as N‑MNIST, CIFAR10‑DVS, DVSGesture, and POKER‑DVS using a convolutional SNN. The work provides detailed, high‑quality datasets for future experiments and validates ANTShapes as a suitable tool for generating event‑based vision data.
arXiv:2607. 27990v1 Announce Type: cross Abstract: Spiking Neural Networks (SNNs) communicate through sparse binary spike events rather than dense activations, enabling energy-efficient inference on neuromorphic hardware and motivating their use in always-on, battery-powered edge systems.
The paper introduces the Sparse-Activation-ReLU (SAR) layer, a single‑step neural operator that promotes activation sparsity without surrogate‑gradient training and is compatible with event‑based computing. In a trunk‑based NOMAD architecture, SAR improves the combined Latency‑Error‑Energy (LEE) metric by over fivefold compared to Variable Spiking Neuron (VSN) and Leaky Integrate‑and‑Fire (LIF) models. Additional techniques such as synthetic knowledge distillation, a ReLU‑based spiking loss, and graph‑neighbor thresholding further reduce LEE and L2 error on the Heat Exchanger dataset, advancing energy‑efficient virtual sensing for edge deployment.
arXiv:2610.00350v1 Announce Type: new Abstract: Spiking Neural Networks (SNNs) offer an energy-efficient approach to processing event-camera data, yet out-of-distribution (OOD) detection remains chal...
arXiv:2608. 03324v1 Announce Type: new Abstract: Federated learning enables collaborative model training across distributed edge devices while strictly preserving data privacy.
arXiv:2608.21764v1 Announce Type: cross Abstract: Event-based vision has emerged as a promising paradigm for energy-aware artificial intelligence (AI), offering sparse, low-latency visual signals tha...
The paper presents a novel multi‑exit computational scheme for TinyML on an ultra‑low‑power GAP9 SoC, adding confidence‑based gating points to a MobileNetV2 CNN for ImageNet‑100. By allowing inference to stop early, the approach cuts average MAC operations by 41 % (from 313 MMAC to 185 MMAC), reduces inference time by 29 % (49 ms to 35 ms), and saves 24 % in energy (2.1 mJ to 1.6 mJ per frame) with only a ~1 % drop in accuracy. Compared to a state‑of‑the‑art adaptive CNN on the same hardware, the method more than doubles computational efficiency, raising MAC/cycle from 8.1 to 17.2.
arXiv:2608. 03589v1 Announce Type: new Abstract: We present a method for designing deep neural networks (DNNs) for intermittent, energy-autonomous, on-device learning on microcontroller units (MCUs).
WARD is a runtime‑adaptive Vision Transformer framework designed for edge AI that combines channel‑wise subnetwork partitioning, reliability‑aware continual learning, and dynamic operating‑mode scheduling. It operates two physically isolated subnetworks across four modes—Full‑Precision, Low‑Power, High‑Reliability, and Adaptive—to balance computational cost and fault tolerance while maintaining uninterrupted inference. Implemented on a lightweight FPGA accelerator with minimal area overhead, WARD achieves a network‑level failure rate of 1.79% under high Bit Error Rates and supports rapid mode transitions within a few clock cycles.
arXiv:2606. 14716v1 Announce Type: cross Abstract: Edge object detection on embedded hardware requires balancing inference latency and detection quality under changing resource pressure.
arXiv:2606. 12287v1 Announce Type: cross Abstract: The Transformer architecture is widely regarded as the most powerful tool for natural language processing, but due to a high number of complex operations, it inherently faces the issue of high energy consumption.