AnalogPortBench is a new benchmark comprising 54 tasks that evaluate how well large language models (LLMs) can port ten analog circuits—from current mirrors to telescopic amplifiers—across process nodes, specifically from a 0.18 µm process to the SKY130 PDK. The tasks vary in difficulty, ranging from straightforward ports to reduced supply and stricter specifications, and include infeasible scenarios; each feasible task has a verified reference design at five process corners. Experiments with six leading LLMs show that while models can handle simple circuit ports, they rarely redesign headroom‑sensitive amplifiers, often miss infeasible specifications, and benefit more from simulation feedback than from additional samples or reasoning steps.
arXiv:2608. 13472v1 Announce Type: cross Abstract: Analog circuit design is a time-consuming, iterative process in a nonlinear and high-dimensional design space that relies heavily on expert intuition.
AnalogScout is a new framework that uses a large language model (LLM) agent to perform PVT-aware analog device sizing more efficiently. By reusing elite designs, applying analytic gm/Id local sizing, and refining globally under full-corner verification, it cuts power consumption by 43.3% compared to the CMA-ES evolution strategy while using the same 16,000 simulations on three SKY130 OTAs. The method also outperforms Bayesian optimization and other LLM-driven flows on the tested OTAs.
arXiv:2602. 00510v2 Announce Type: replace Abstract: Most LLM code-synthesis benchmarks rely on unit tests as the reward oracle, but PCB schematic design has none: correctness is defined by structured physical constraints over real IC packages and pin-level assignments, per-task golden references are unavailable, and SPICE simulation does not validate schematic-level correctness.
Large Language Models (LLMs) are increasingly used to optimize code for performance, but this study shows that such optimizations often increase energy consumption rather than reduce it. Across 11 open‑source models and 1,000 benchmark problems, inference energy ranged from 0.79 to 8.68 MJ, and 42 of 44 configurations produced code that used 4% to 886% more energy than human‑written reference solutions. Mixture‑of‑Experts architectures and token‑limit constraints can reduce inference energy, yet performance‑optimized code remains energy‑heavier, indicating that speed and sustainability are not always aligned goals.
arXiv:2607. 13416v1 Announce Type: new Abstract: Automating analog circuit topology design is essential to reduce the extensive manual effort required to meet increasingly diverse and customized application demands.
arXiv:2508. 10409v3 Announce Type: replace-cross Abstract: This paper constructs a textual dataset for training large language models (LLMs) to learn analog circuit knowledge and customizes LLM training techniques.
arXiv:2607. 03701v1 Announce Type: cross Abstract: Large language models (LLMs) can propose circuit-optimization decisions, but industrial analog flows cannot expose foundry PDK content, proprietary schematics, absolute simulation paths, or license-bound tool state to a cloud endpoint.
arXiv:2606. 12983v1 Announce Type: new Abstract: Automated testbench generation has become a critical bottleneck in large language model (LLM)-driven Register Transfer Level (RTL) workflows, where large numbers of candidate designs must be verified rapidly and reliably.
arXiv:2608. 12197v1 Announce Type: cross Abstract: Large Language Models (LLMs) are increasingly used in circuit design workflows, yet their reliability on simulator-facing SPICE netlist recognition and manipulation remains poorly understood and is rarely separated from high-level design reasoning.
PerfReasoning is a new benchmark that tests large language models (LLMs) on their ability to reason about hardware performance and generate analytical performance‑model code. The benchmark presents workloads, architectures, and mapping specifications, asking models to compare mappings and predict off‑chip traffic and buffer requirements. While the best closed‑source models achieve over 90% accuracy on reasoning‑based Q&A and the top open‑weight model scores 82.4%, constructing full performance models remains difficult, with most models scoring below 15% and significant variability across runs. Task‑specific reinforcement learning can improve a 4B model’s mapping‑reasoning accuracy by 15.7 points, but feedback‑free self‑revision prompting is not reliably effective.
Analog-DB is an open‑source, versioned database that stores analog integrated circuit designs in a process‑neutral topology, reusable testbenches, and machine‑readable datasheets using a domain‑specific language. The database’s parameterization scheme and schema‑governed contracts enable AI design agents to discover, compose, and retarget circuits across multiple process kits. In a case study, a coding agent used the released artifacts to size op‑amp cores for a chopper instrumentation amplifier, uncovering defects that a sizing‑only baseline missed.
The paper introduces LOADBench, a large open dataset and benchmark suite for machine learning in analog integrated circuit design. It contains over 100 operational amplifier topologies from the SkyWater130 PDK, each with detailed annotations, sizing constraints, testbenches, and thousands of Pareto-optimal sizing-performance pairs generated by NSGA-II. Six standardized benchmark tasks—inverse sizing, topology selection, sub‑circuit classification, structural circuit generation, Pareto‑membership prediction, and multi‑objective optimization—are defined with precise protocols, and all data, annotations, and reference implementations are released under an open license.