RACE-AIMC is a framework that selects a single analog in‑memory computing (AIMC) accelerator from a pool to meet a specified energy budget while providing a mathematically exact upper bound on its error rate. Offline, it evaluates each chip, chooses the best one, and computes the bound; online, only that chip runs and a lightweight check decides whether to accept its output or defer to a fallback. Simulations show the certified error stays below 10% (mean 7.83%) and the system achieves clean‑digital accuracy while reducing energy use by about 69% compared to running all chips.
arXiv:2510. 16028v4 Announce Type: replace-cross Abstract: Neural networks increasingly run on hardware outside the user's control (cloud GPUs, inference marketplaces).
The paper evaluates coreset selection methods by incorporating both selection and training time into a unified wall‑clock budget, using a standardized benchmark across four datasets and multiple selectors. Across numerous budget anchors, simple random or full‑data training consistently outperforms sophisticated selectors, and selection costs are dominated by a full‑dataset scan that cannot be amortized. The study also identifies when subset reuse can justify selection and reports several correctness fixes in a popular codebase.
The paper investigates how temperature affects analog deep neural network (DNN) inference, focusing on both stochastic and systematic non‑idealities in analog hardware. Experiments show that temperature‑induced performance loss is mainly driven by systematic errors rather than random noise. The study evaluates various mitigation techniques, finding that noise‑aware training and temperature‑aware calibration—especially hardware‑in‑the‑loop training—best preserve inference accuracy across different thermal conditions.
arXiv:2606. 17249v1 Announce Type: cross Abstract: The dominant trajectory of modern machine learning has been to scale up: larger models, larger accelerators, larger memory budgets.
Code models strictly prioritize functional correctness, leaving software energy efficiency as an unoptimized byproduct. Training models to generate energy-efficient code requires reproducible feedback at scale, which physical hardware measurement cannot reliably provide due to variance.
arXiv:2608. 08020v1 Announce Type: new Abstract: Test-time compute scaling is a primary driver of performance in large reasoning models (LRMs), but extreme inefficiency bounds current approaches, shifting the critical question from \emph{how much} compute to spend, to \emph{where} to allocate it.
arXiv:2607. 04577v1 Announce Type: new Abstract: Code models strictly prioritize functional correctness, leaving software energy efficiency as an unoptimized byproduct.
The paper presents a Pareto atlas of LLM inference optimizations, mapping cost, quality, and latency trade‑offs for Qwen2.5‑7B‑Instruct on L4, A100, and H100 GPUs. Using 54 measured configurations and a calibrated simulator, it identifies 18 of 36 setups on the Pareto frontier, showing that combined methods outperform single ones. Quality tests reveal that AWQ 4bit and FP8 weights offer significant latency reductions while largely preserving accuracy, but naive FP8 KV caching fails to answer any questions correctly.
arXiv:2608. 05944v1 Announce Type: cross Abstract: We report operational experience full-fine-tuning a 32.
The paper proposes DCO, a dynamic cache orchestration scheme for multi-core AI accelerators that uses application-aware policies and dataflow information to guide cache replacement, bypass decisions, and thrashing mitigation. Using a cycle-accurate simulator, the authors demonstrate up to 1.80× speedup over conventional cache architectures and validate the approach with an analytical model and RTL implementation. The design occupies 0.064 mm² on a 15 nm process and operates at 2 GHz, showing that a shared system-level cache can simplify programming while boosting performance for large language model workloads.
arXiv:2606. 11348v1 Announce Type: new Abstract: Clock Tree Synthesis (CTS) is a computationally expensive stage in the physical design flow, requiring iterative EDA tool invocations to navigate a vast configuration space for optimal power, wirelength, and timing skew.
arXiv:2209. 00188v4 Announce Type: replace-cross Abstract: Long-latency load requests continue to limit the performance of high-performance processors.