Taming Speculative Search for Test-Time Scaling in LLM Serving
Read the original on arXiv Computation and Language →The Flow has not summarised this story yet — read it at arXiv Computation and Language.
The Flow has not summarised this story yet — read it at arXiv Computation and Language.
arXiv:2608. 08020v1 Announce Type: new Abstract: Test-time compute scaling is a primary driver of performance in large reasoning models (LRMs), but extreme inefficiency bounds current approaches, shifting the critical question from \emph{how much} compute to spend, to \emph{where} to allocate it.
The paper introduces Planned Test-Time Scaling (PTTS), a method that replaces independent sampling of reasoning branches with a coordinated joint policy. PTTS uses a planner to generate distinct solution outlines for each branch and an executor to produce full solutions, thereby improving coverage of complementary reasoning modes. Two variants—PTTS‑ZS (zero‑shot) and PTTS‑RL (reinforcement‑learned)—demonstrate significant gains on five mathematical reasoning benchmarks, with PTTS‑RL achieving up to a 13.4‑point improvement in pass@64 over repeated sampling.
arXiv:2510. 22228v2 Announce Type: replace-cross Abstract: Layer pruning has emerged as a widely adopted technique for improving the efficiency of large language models (LLMs).
The paper introduces SWE-Flux, a repository‑level benchmark designed to test large language models’ ability to reason about runtime behavior. It contains 480 execution‑grounded instances from 12 real Python repositories, with gold answers automatically harvested from instrumented test executions. Evaluation of five LLMs shows the task remains difficult, with the best model achieving only 37% accuracy, and the benchmark can generate challenging variants through input perturbation.
arXiv:2608. 04001v1 Announce Type: cross Abstract: Large language models can solve substantially harder reasoning problems with more inference-time compute.
arXiv:2606. 08976v1 Announce Type: new Abstract: LLM-based RTL generation and reasoning is a promising direction for hardware design automation.