arXiv AI
Aug 10

HLSmith: An Expert-Guided Agentic Framework for C/C++-to-HLS Translation

arXiv:2608. 06791v1 Announce Type: cross Abstract: Application-specific FPGA accelerators offer substantial performance and energy-efficiency gains across many application domains, but developing them is costly, often requiring months of specialized effort.

By Yuebo Luo, Ahmad Sedigh Baroughi, Philip Stachura, Le Chen, Venkatram Vishwanath, Zhenman Fang, Caiwen Ding
arXiv AI
Jul 21

CLOSER-Bench: Evaluating Budgeted Cross-Stage Design Closure for Hardware Agents

arXiv:2607. 16632v1 Announce Type: cross Abstract: Hardware engineering exposes coding agents to a form of long-horizon work that is difficult to capture with pass-at-k: progress is continuous, tool feedback is delayed and heterogeneous, and a backend failure may require revising RTL rather than tuning another physical-design parameter.

By Peilong Zhou, Zhirong Chen, Cangyuan Li, Haoyu Gao, Kaiyan Chang, Ziming Qu, Ying Wang
arXiv AI
Sep 21

Can Agents Design Better Chips with a Higher Level Abstraction?

Large Language Model agents are being explored for chip design, but most methods work directly at RTL. This study compares Direct RTL Design, Agent-based HLS Design, Post-Compiler HLS Refinement, and Post-HLS RTL Refinement, and proposes a combined workflow called Agent-based HLS with RTL Refinement (AHRR). Using FPGAs for evaluation, AHRR achieves a 2.6× geometric‑mean speedup over Direct RTL Design across an 11‑task benchmark suite, demonstrating that higher‑level abstractions and subsequent RTL refinement can improve chip design efficiency.

By Zijian Ding, Yang Zou, Yizhou Sun, Jason Cong