arXiv:2608. 13767v1 Announce Type: new Abstract: Analog IC layout design remains a labor-intensive iterative process dominated by simulation-driven refinement.
By Bingyang Liu, Ziming Wei, Xiaohan Gao, David Z. Pan
arXiv:2607. 13416v1 Announce Type: new Abstract: Automating analog circuit topology design is essential to reduce the extensive manual effort required to meet increasingly diverse and customized application demands.
By Guanglei Zhou, Chen-Chia Chang, Yikang Shen, Jonathan Ku, Isaac Jacobson, Jingyu Pan, Yiran Chen, Xin Zhang
arXiv:2608. 13472v1 Announce Type: cross Abstract: Analog circuit design is a time-consuming, iterative process in a nonlinear and high-dimensional design space that relies heavily on expert intuition.
By Mohammed Ayman Habib, Rylan Hart, Morteza Fayazi
arXiv:2607. 14165v1 Announce Type: cross Abstract: While Large Language Models (LLMs) have demonstrated significant capability in software code generation, their application to analog Electronic Design Automation (EDA) is bottlenecked.
By Dimple Vijay Kochar, Hae-Seung Lee, Anantha P. Chandrakasan
Analog circuit sizing remains a challenging and time-consuming task due to the large design space, strong performance trade-offs, and increasing circuit complexity in scaled technologies. Although rec...
ATLAS is an embedding‑guided quality‑diversity framework that enables scaffold‑free synthesis of full algorithms for combinatorial optimization using large language models. It allows the LLM to freely choose, restructure, and control algorithm components while automatically detecting and repairing execution, interface, and feasibility failures. Across four NP‑hard problems, ATLAS outperforms state‑of‑the‑art component‑synthesis methods and remains competitive with strong human‑designed algorithms, demonstrating that a larger design space can be practically searched.
By Danial Yazdani, Mohammad Nabi Omidvar, Yuan Sun, Maksud Ibrahimov, Xiaodong Li