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LLM Agent-Based Design of RISC-V CPUs with FPGA-in-the-Loop Evaluation

The paper introduces a development environment where large language model (LLM) agents design RISC‑V CPUs that are implemented on an FPGA for real‑time performance evaluation. Using on‑board measurements, the approach guides design decisions and accelerates evaluation, achieving a 9.6× speedup over single‑threaded RTL simulation. In a case study, FPGA measurements uncovered long‑run performance degradation that short diagnostic runs missed, leading to candidate selection, root‑cause analysis, and a fix.

Breaking the Ice: Analyzing Cold Start Latency in vLLM

arXiv:2606. 07362v1 Announce Type: new Abstract: As scalable inference services become popular, the cold start latency of an inference engine becomes important.

No GPU left behind: Unlocking Efficiency with Co-located vLLM in TRL

VLA-HWBench: Where the Time Goes When VLA Models Run on Edge Hardware

arXiv:2610.34717v1 Announce Type: cross Abstract: Vision--language--action (VLA) models increasingly run on edge devices aboard robots, where inference latency constrains closed-loop robot control. H...

The Energy Blind Spot: NVIDIA's Flagship Edge AI Hardware Cannot Support Process-Level Energy Attribution

arXiv:2605. 27599v2 Announce Type: replace-cross Abstract: Agentic AI workloads - where a single user goal triggers multi-step orchestration, tool calls, retries, and failure recovery - are being targeted for edge deployment, with NVIDIA, Dell, HP, ASUS, MSI, Acer, and Gigabyte all shipping GB10-based desktop AI systems in 2026.

KernelGenBench: A Multi-Source and Multi-Chip Benchmark for LLM-based Kernel Generation

arXiv:2607. 27231v1 Announce Type: cross Abstract: Large language models (LLMs) have significantly increased the demand for efficient accelerator kernels, but kernel development remains a highly specialized and labor-intensive task.