This survey reviews over 100 studies on implementing reinforcement learning (RL) on field‑programmable gate arrays (FPGAs) and integrated circuits (ICs), covering a wide range of RL families from model‑based Markov decision processes to deep RL and multi‑agent methods. It organizes the literature by abstraction level, hardware realization strategy, and application domain, and evaluates key metrics such as resource utilization, latency, throughput, and power consumption. The paper identifies common architectural patterns, practical limitations, and open research challenges, offering a unified reference for researchers developing RL‑driven hardware systems.
By Hamza Kheddar
arXiv:2512. 22560v2 Announce Type: replace-cross Abstract: Agentic Reinforcement Learning (RL) trains LLMs through multi-turn interactions with environments, producing workloads that mix compute-bound prefill, bandwidth-bound decoding, CPU-heavy environment execution, and bursty reward evaluation.
By Wei Gao, Yuheng Zhao, Tianyuan Wu, Shaopan Xiong, Weixun Wang, Dakai An, Lunxi Cao, Dilxat Muhtar, Zichen Liu, Haizhou Zhao, Ju Huang, Siran Yang, Yongbin Li, Wenbo Su, Jiamang Wang, Lin Qu, Bo Zheng, Wei Wang
arXiv:2609.24456v1 Announce Type: cross
Abstract: Distributed reinforcement learning (RL) scales training by parallelizing actors and learners around an Experience Buffer. As RL workloads grow, howev...
By Sitong Zhang, Tuo Shi, Mario Di Francesco, Zeke Wang, Bo Zhao
ReFlow is a system‑algorithm co‑designed framework for efficient reinforcement learning (RL) post‑training of large language models (LLMs). It introduces replay‑driven decoupling, allowing recent trajectories to be reused multiple times to amortize rollout costs while limiting policy staleness. The architecture features a dual replay cycle, an elastic resource pool, and an adaptive scheduler, achieving up to 2.06× higher training throughput compared to existing synchronous and asynchronous RL systems without sacrificing model performance.
By Yukun Tian, Junwei Su, Haofeng Xu, Lansong Diao, Zhengping Qian, Weibo Zhao, Wenchao Zhou, Ruiting Zhou, Chuan Wu
arXiv:2605. 26418v2 Announce Type: replace-cross Abstract: A properly calibrated rule-based autoscaler can beat every one of six mainstream deep reinforcement learning (DRL) algorithms on cost across every workload we test - so when, if ever, does DRL actually help?
By Guilin Zhang, Chuanyi Sun, Kai Zhao, Shahryar Sarkani, John Fossaceca
arXiv:2606. 24340v1 Announce Type: new Abstract: In recent years, the Internet of Things (IoT) paradigm has been shifting toward batteryless, energy-harvesting architectures.
By Samer Nasser, Henrique Duarte Moura, Ritesh Kumar Singh, Maarten Weyn, Jeroen Famaey
In recent years, the Internet of Things (IoT) paradigm has been shifting toward batteryless, energy-harvesting architectures. Sustaining reliable operation in these systems requires intelligent management of highly volatile stored energy.
arXiv:2609.13243v1 Announce Type: cross
Abstract: We present GzDRL, a novel single-process reinforcement learning (RL) framework for Gazebo that overcomes longstanding bottlenecks in scalable, reprod...
By Amal Dev Haridevan, Junjie Kang, Jinjun Shan
arXiv:2511. 07046v4 Announce Type: replace-cross Abstract: Deploying continuous-control reinforcement learning policies on embedded hardware requires meeting tight latency and power budgets.
By Fabian Kresse, Christoph H. Lampert
arXiv:2609.36393v1 Announce Type: cross
Abstract: Traditional reinforcement learning (RL) techniques focus on maximizing expected cumulative reward, where each action assumes to take a constant unit...
By Muhang Tian, Sherry Yang
arXiv:2604.19146v2 Announce Type: replace
Abstract: Particle accelerator beamline optimization is a high-dimensional control problem traditionally requiring significant expert intervention. We presen...
By Anwar Ibrahim, Fedor Ratnikov, Maxim Kaledin, Alexey Petrenko, Denis Derkach
arXiv:2607. 14008v1 Announce Type: new Abstract: In this paper, we introduce Lighthouse RL, a sample-efficient reinforcement learning (RL) approach for analog circuit sizing.
By Mustafa Emre G\"ursoy, Stefan Uhlich, Ryoga Matsuo, Ya\u{g}{\i}z Gen\c{c}er, Arun Venkitaraman, Chia-Yu Hsieh, Andrea Bonetti, Eisaku Ohbuchi, Lorenzo Servadei