Certified Circuits introduces a framework that wraps any black‑box circuit discovery algorithm with randomized data subsampling to provide provable stability guarantees. By certifying that inclusion decisions over circuit components are invariant to bounded edit‑distance perturbations of the concept dataset, unstable components are abstained from, producing more compact and accurate mechanistic explanations. Across ResNet, ViT, and GPT‑2 on vision and language tasks, Certified Circuits achieves up to 56% higher accuracy and up to 80% fewer components, maintaining reliability where baseline methods degrade.
arXiv:2607. 18921v1 Announce Type: cross Abstract: Circuit extraction identifies a small set of model components whose presence preserves a target behavior under ablation, and the resulting circuit is often read as the mechanism behind that behavior.
arXiv:2605. 26343v2 Announce Type: replace Abstract: Mechanistic interpretability seeks to explain a model's behaviour by finding its circuit: the sparse subgraph of the model's computation that is causally responsible for it.
arXiv:2608. 08536v1 Announce Type: new Abstract: Circuit localization is a mechanistic interpretability task whose goal is to identify a sparse subgraph of a transformer's computation graph sufficient to reproduce a particular behavior.
The paper introduces TopKLoRA, an interpretable parameter‑efficient fine‑tuning method that activates only the top‑k adapter latents per token. Using this sparse LoRA, the authors fine‑tune large language models on a poisoned dataset, identify and ablate the minimal circuit responsible for a backdoor, and show that the resulting circuits are an order of magnitude smaller than dense LoRA baselines. They also demonstrate how to construct model organisms with localized circuits via gradient‑routing, supporting the development of interpretable‑by‑design architectures.
arXiv:2605.09129v2 Announce Type: replace Abstract: Circuit study aims to explain how language models (LMs) implement a task by localizing and interpreting a circuit: a computational subgraph respons...
Certified Mechanistic Edits: Behavioral Guarantees for Skill Removal and Preservation proposes a method to formally certify that disabling a specific circuit in a neural network removes a targeted skill while preserving another, for every input within a continuous region. The approach extends beyond testing by providing sound guarantees over continuous embedding-space regions, demonstrated on toy ReLU networks and a standard transformer. It also shows that no finite deterministic black-box test can guarantee removal, highlighting the necessity of formal verification.
arXiv:2605. 24033v2 Announce Type: replace Abstract: Mechanistic interpretability typically discovers circuits and then argues what they do from examples and ablations.
ReDIL-GNN is a framework for resynthesis domain‑incremental learning in circuit graph neural networks. It adapts a fixed prediction or representation head as new synthesis styles appear and evaluates retention across all previously seen domains. The method introduces the Resynthesis Adaptability Index (RAI), a pre‑adaptation score that combines adaptation need, source‑equivalence recoverability, structural coverage, and update compatibility to decide whether to adapt, reuse, or defer updates.
The paper introduces Circuit Condensation, a post‑training method that prunes low‑attribution edges from large causal graphs and trains a low‑rank adapter to preserve behavior. Across four behaviors and eight models, the condensed circuits are on average 8.1× smaller than the strongest frozen baseline, with reductions up to 316×. Experiments show that weight updates drive the size reduction, and detailed ablations reveal dependencies among remaining edges and a more focused set of heads for indirect object identification.
arXiv:2609.36813v1 Announce Type: new Abstract: Large language models (LLMs) exhibit strong general capabilities that mechanistic interpretability has attributed to sparse computational circuits. How...
The paper introduces a circuit‑grounded framework that links training‑dynamics‑based data valuation with mechanistic interpretability. It defines data quality along learnability, challenge, and alignment, identifies internal model circuits that control these utilities, and uses them as controllable interfaces for data generation. The authors present SAMS, a stage‑aware scheduling method that steers circuit‑guided data to match the model’s evolving optimization needs, achieving more diverse and effective data than prompt‑based baselines on multiple‑choice QA tasks.
arXiv:2607. 19317v1 Announce Type: new Abstract: Circuit analysis can support not only model explanation but also downstream interventions such as pruning, editing, steering, and selective fine-tuning.