DataKernelBench evaluates whether large language models (LLMs) can optimize database queries for GPU execution. The benchmark translates SQL into PyTorch TorchPlan programs and tests LLMs on optimizing core tensor snippets or full queries in CUDA or Triton, using execution-guided repair. On TPC‑H SF10 with an H100 GPU, the best full‑query CUDA configuration outperforms torch.compile by 2.11×, and extending TorchPlan with Dask‑cuDF enables a 2.54× speedup on TPC‑H SF100 across four H100 GPUs.
By Gokul Karthik Kumar, Yotam Perlitz, Corey Lammie, Andrea Giovannini, Katja Hose
arXiv:2604. 01489v2 Announce Type: replace Abstract: High-performance GPU kernels are critical to modern machine learning systems, yet developing them remains a manual, expert-driven process.
By Tara Saba, Zhiyang Chen, Jikai Jason Li, Anne Ouyang, Xujie Si, Fan Long
AMDKernelVault is an open HIP and Triton kernel corpus and training framework designed for AMD CDNA GPUs. It includes 62,153 verified HIP kernels, 39,893 Triton kernels, and 2,377 ROCm library QA entries, and introduces agent-driven pipelines (HIPKernelGen and TritonKernelGen) that convert PyTorch references into GPU kernels, compile, validate, and profile them on AMD hardware. The corpus was used to fine‑tune Qwen3-8B, achieving the highest correctness on several benchmarks such as PyTorch-to-HIP, TritonBench‑G, and ROCmBench under fixed evaluation budgets.
By Ji Liu, Saptarshi Majumder, Yiqing Huang, Wenwen Ouyang, Umang Pandey, Zeping Li, Chushi Chen, Zihao An, Puyuan Yang, Zekai Li, Sina Rafati, Ziqiong Liu, Pratik Prabhanjan Brahma, Dong Li, Zicheng Liu, Sharon Zhou, Emad Barsoum
arXiv:2604. 23466v2 Announce Type: replace Abstract: NVIDIA's CUDA Tile (CuTile) introduces a Python-based, tile-centric abstraction for GPU kernel development that aims to simplify programming while retaining Tensor Core and Tensor Memory Accelerator (TMA) efficiency on modern GPUs.
By Divakar Kumar Yadav, Tian Zhao, Deepak Kumar
arXiv:2607. 16241v1 Announce Type: cross Abstract: Recent large language models (LLMs) can generate custom CUDA kernels that appear to outperform PyTorch on benchmarks such as KernelBench.
By Yunxiang Zhang (Xiangjun), Ping Yu (Xiangjun), Jianyu Wang (Xiangjun), Max (Xiangjun), Fan, Julian Reed, Azalia Mirhoseini, Will Su
arXiv:2607. 14541v1 Announce Type: new Abstract: Existing GPU kernel generation benchmarks draw problems from synthetic or curated sources that diverge from deployed workloads.
By Lingyun Yang, Yuxiao Wang, Shenghao Liang, Linfeng Yang, Daocheng Ying, Chunbo You, Rui Zhang, Luping Wang, Yinghao Yu, Guodong Yang, Liping Zhang
KernelArc is a multi-agent framework designed to autonomously optimize GPU kernels across diverse workloads. It employs strategy-specialized agents that run concurrently, coordinating via conclusions-only shared memory, a deterministic benchmark guard, and read-only cross-agent state with plateau-triggered drafting. Evaluated on NVIDIA H100 and B200 GPUs with SOL-ExecBench workloads, KernelArc produced top-ranked implementations for tasks such as BF16 GEMM, cuBLASLt configuration tables, and various attention mechanisms, achieving first place on several leaderboard categories.
By Joyjit Kundu, Ben Stoffelen, Kaili Wang, Peter Vrancx, Ludovic Denoyer
arXiv:2608. 02611v1 Announce Type: cross Abstract: Automating GPU kernel optimization remains difficult in practice: generated variants can violate correctness constraints, runtime measurements are noisy, and search often stalls early.
By Shuai Che, Gang Peng
arXiv:2608. 05033v1 Announce Type: cross Abstract: Sparse matrix kernels are fundamental to scientific computing, graph analytics, and machine learning.
By Shiyang Li, Guangyan Sun, Jinwei Tang, Yanzhi Wang, Mingyi Hong, Caiwen Ding
Figure 1: CUDA-to-MLX optimization translation map. CUDA optimization knowledge can be translated into architecture-native MLX strategies rather than copied instruction-for-instruction.