arXiv Machine Learning By Silviu S. Craciunas, Christian Hakert, Jian-Jia Chen, Zden\v{e}k Hanz\'alek, Paul Pop

Schedulable Job-Level Dependencies for Cause-Effect Chains via Graph Neural Networks

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arXiv:2607. 02624v1 Announce Type: cross Abstract: Modern automotive software architectures comprise large sets of mixed-criticality functions executing on shared multi-core platforms with strict real-time and end-to-end timing requirements.

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arXiv AI
Jun 16

A Learning Method with Gap-Aware Generation for Heterogeneous DAG Scheduling

arXiv:2603. 23249v2 Announce Type: replace-cross Abstract: Efficient scheduling of directed acyclic graphs (DAGs) is a core problem in large-scale data-intensive computing systems, where query plans, data-processing workloads, and computation graphs consist of dependent tasks competing for limited heterogeneous resource pools.

By Ruisong Zhou, Haijun Zou, Li Zhou, Chumin Sun, Zaiwen Wen
arXiv AI
Sep 17

Variational Approach for Job Shop Scheduling

The paper introduces Variational Graph-to-Scheduler (VG2S), a framework that applies variational inference to the Job Shop Scheduling Problem (JSSP). By decoupling representation learning from policy optimization using a variational graph encoder and an ELBO-based objective, VG2S improves training stability and robustness to hyperparameter changes. Experiments show that VG2S outperforms state‑of‑the‑art deep reinforcement learning baselines and traditional dispatching rules, especially on large‑scale benchmark instances such as DMU and SWV.

By Seung Heon Oh, Jiwon Baek, Hyunjin Oh, Kiyoung Cho, Heechang Yoon, Jong Hun Woo
arXiv AI
Sep 4

LevelSyn: Physical-Aware Logic Synthesis via Level-Asynchronous Graph Neural Networks

LevelSyn is a physical-aware logic synthesis framework that uses a level-asynchronous Graph Neural Network to predict high-fidelity gate coordinates by learning the structural and directional semantics of And-Inverter Graphs. It incorporates a level-aligned subgraph partitioning strategy to manage industrial-scale designs and integrates these spatial insights into a new synthesis engine within the Berkeley ABC framework. Experiments on the EPFL benchmark suite show LevelSyn outperforms state-of-the-art methods, achieving an average power reduction of 6.89%, a timing delay improvement of 27.48%, and a 99.59% reduction in design rule check violations.

By Jingyi Zhou, Zhengyuan Shi, Ziyang Zheng, Qiang Xu