Intelligent Identification and Repair of Design Defects in BIM via Domain-Specific Large Language Models
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The paper investigates hallucination in large language model–based automated program repair (APR). It defines hallucination as producing patches or intermediate artifacts that are not grounded in available repair evidence, and analyzes it across final patches and intermediate tasks such as triggering test case identification, line coverage prediction, and additional test case generation. Experiments on 832 Defects4J bugs show that only 21.0%–55.9% of patches pass the developer test suite, with 72.7% of sampled repairs exhibiting hallucinations, often due to incorrect causal localization or repair strategies.
SysML v2's textual syntax enables compiler-based validation of model structure and language conformance. However, semantic mistakes that preserve syntactic validity but violate domain rules cannot be detected through compilers.
arXiv:2606. 03628v1 Announce Type: cross Abstract: Large language models (LLMs) have achieved remarkable progress in open-ended text generation, yet they remain prone to hallucinating incorrect or unsupported content, which undermines their reliability.
arXiv:2606. 03331v1 Announce Type: cross Abstract: Consumer device repair is an important but underexplored testbed for large language models (LLMs).
The paper investigates configuration problems in Retrieval-Augmented Generation (RAG) systems, which combine large language models with components like vector or graph databases. An empirical study of 654 real-world issues from 10 RAG systems categorizes symptoms, root causes, stages, and fix patterns, revealing that symptoms often appear early or late in the pipeline while root causes may lie elsewhere. The authors also offer nine actionable insights for practitioners to test, localize, and resolve configuration issues in RAG systems.
arXiv:2606. 05680v1 Announce Type: cross Abstract: Recent advances in large language models (LLMs) have enabled the automatic synthesis (generation) of register-transfer level (RTL) code from natural language instructions, offering a promising pathway to accelerate chip design.