arXiv Machine Learning
Holographic Invariant Storage: Design-Time Safety Contracts via Vector Symbolic Architectures
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arXiv Machine Learning
Sep 29
Deterministic Regime Switching and Feasibility Inversion in Dynamic Tensor Rematerialization
The paper reports fine‑grained, deterministic instability in Dynamic Tensor Rematerialization (DTR), an online eviction policy for memory‑constrained DNN training. On an LSTM trace, tiny changes in memory budget (0.10% of peak) switch the system between fast and slow execution regimes with up to 7.3× overhead differences, driven by repeated re‑eviction of the same storages. On a ResNet‑32 trace, a deterministic feasibility inversion is observed: the run is feasible at a 0.101 budget ratio, infeasible (OOM) between 0.102–0.106, and feasible again from 0.107, caused by a fully pinned recursive rematerialization frontier exceeding the budget after all evictable tensors are removed. The authors attribute the LSTM instability to the joint size‑staleness scoring term and argue that these represent two distinct budget‑sensitive pathologies rather than a single mechanism.
arXiv Machine Learning
Jul 9
Fractal KV-Cache Archives: Lossless Symbolic Storage with In-Place Retrieval for Long-Context LLM Inference
arXiv:2607. 07144v1 Announce Type: new Abstract: The key-value (KV) cache dominates the memory cost of long-context autoregressive inference, and a growing body of work compresses it through quantization, eviction, or offloading.
arXiv Machine Learning
Aug 6
Forgetful Attention: An Auditable Support-Vector Memory for Selective Retention and Verified Deletion
arXiv:2607. 12204v2 Announce Type: replace Abstract: Auditable memory requires a precise contract: which output is preserved, relative to which reference solve, and across which updates.
arXiv Machine Learning
Jul 7
SABLE: An NDA-Safe Closed-Loop LLM Framework for Analog Circuit Optimization in Industrial EDA Flows
arXiv:2607. 03701v1 Announce Type: cross Abstract: Large language models (LLMs) can propose circuit-optimization decisions, but industrial analog flows cannot expose foundry PDK content, proprietary schematics, absolute simulation paths, or license-bound tool state to a cloud endpoint.
arXiv Machine Learning
Sep 24
Risk-Controlled KV-Cache Eviction: From Memory Budgets to Risk Targets
arXiv:2609.27981v1 Announce Type: cross Abstract: KV-cache eviction is typically evaluated through average quality-memory trade-offs, yet a small average loss can hide requests whose utility degrades...
arXiv AI
Aug 7
Runtime Observability for Heterogeneous Attention Memory
arXiv:2608. 05863v1 Announce Type: new Abstract: Modern models no longer keep a plain KV cache: latent caches, learned sparse selectors and recurrent states each carry the model's memory in a different form, and each fails differently under compression.