Efficient Controllable Generation for SDXL with T2I-Adapters

Exploring simple optimizations for SDXL

HighTide: An Agent-Curated Open-Source VLSI Benchmark Suite

arXiv:2606. 04126v1 Announce Type: cross Abstract: We introduce HighTide, an evolving AI-assisted benchmark suite.

SDXL in 4 steps with Latent Consistency LoRAs

Accelerating SD Turbo and SDXL Turbo Inference with ONNX Runtime and Olive

LP5X-PIM Sim: A High-Fidelity HW/SW Integrated Simulator for LPDDR5X-PIM

arXiv:2606. 00636v1 Announce Type: cross Abstract: This tech note describes the architecture and execution results of the LPDDR5X-PIM simulator, developed by Samsung Electronics.

QiMeng-ChipV-RTL: Exploiting Information Locality for IP-level Verilog Generation

QiMeng-ChipV-RTL is a multi‑agent framework that tackles the challenges of generating Register‑Transfer Level (RTL) code for industrial IP‑level hardware design. By partitioning long design documents into short, localized tasks and using hierarchical planning, localized code generation, interface‑consistent merging, and AST‑guided debugging, it scales to complex specifications. Experiments on the RealBench benchmark show ChipV-RTL achieves a 45.0% pass rate, outperforming state‑of‑the‑art LLMs and agents which reach only 21.6%.