arXiv Machine Learning
Bern2Edge: A Neurosymbolic Compiler for Edge Deployment via Bernstein Polynomial Networks
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arXiv Machine Learning
Jul 8
BitLogic: Training Framework for Gradient-Based FPGA-Native Neural Networks
arXiv:2602. 07400v2 Announce Type: replace Abstract: Gradient-based LUT- and logic-gate-based neural networks (LUTNet, LogicNets, DiffLogic, PolyLUT, NeuraLUT, WARP-LUT, DWN, LILogicNet, LightLUT) replace multiply-accumulate arithmetic with Boolean lookups.
arXiv Machine Learning
Sep 17
FAME: An FPGA-Based Platform for Approximate Multipliers Evaluation with Pattern-Guided DNN Retraining
FAME is an FPGA-based platform that evaluates approximate multipliers directly in hardware, eliminating slow CPU/GPU LUT emulation and reducing evaluation time for DNN inference. It also introduces a pattern-guided retraining method that uses multiplier-specific patterns to recover accuracy losses. Experiments on ResNet‑18 and MobileNetV2 over ImageNet show up to 3.47× faster multiplier evaluation and a 65.5% accuracy improvement over prior retraining approaches.
arXiv Machine Learning
Jun 19
Low-Energy Reduced RISC-V Instruction Subset Processor for Tsetlin Machine Inference at the Edge
arXiv:2606. 19964v1 Announce Type: new Abstract: Tsetlin Machine (TM) is a logic-based machine learning approach that relies on simple bitwise operations and finite-state automata, which makes it attractive for edge AI deployments.
arXiv Machine Learning
Aug 28
Pruning Binarized Neural Networks: A Dedicated Framework and Globally Weighted Algorithms
The paper presents a PyTorch-based framework for designing and optimizing binarized neural networks, incorporating freezing and pruning mechanisms. It introduces a novel pruning method that uses a global weighting scheme to assess parameter importance across abstraction levels, achieving a 70% pruning rate on VGG11 without sacrificing accuracy—outperforming existing binarized pruning results of 41%. The framework facilitates rapid, reproducible evaluation and prototyping of state‑of‑the‑art binarized network techniques.
arXiv Machine Learning
Jul 10
FPGN: Redefining Ultra-Fast Programmable Gate-based Neural Acceleration with Differentiable LUTs
arXiv:2607. 08427v1 Announce Type: cross Abstract: Achieving nanosecond-scale inference latency for deep neural networks (DNNs) has become a primary architectural concern for latency-critical applications.
arXiv AI
Jun 16
NeuronFabric: A Software Reference Architecture for On-Chip Transformer Training with Local Adam
arXiv:2606. 16440v1 Announce Type: cross Abstract: Publicly documented accelerator architectures generally separate training computation from optimizer-state updates or rely on external memory and host orchestration.