Benchmarking Language Model Performance on 5th Gen Xeon at GCP

Fine-Tuning and Serving Gemma 4 31B on Google Cloud TPU: A Technical Comparison with GPU Baselines

arXiv:2605. 25645v2 Announce Type: replace-cross Abstract: We present the first end-to-end demonstration of fine-tuning and serving Google's Gemma 4 31B model on TPU hardware, providing an empirical comparison of TPU and GPU platforms for large language model adaptation.

AMD + 🤗: Large Language Models Out-of-the-Box Acceleration with AMD GPU

ParBench: A Benchmark for Reliable Evaluation of LLM Parallel Code Translation

arXiv:2607. 22588v1 Announce Type: new Abstract: Modern compute-intensive software must migrate across a changing ecosystem of accelerators, programming APIs, compiler stacks, and portability layers, including CUDA, OpenMP, OpenCL, and OpenMP target offload.

CodegenBench: Can LLMs Write Efficient Code Across Architectures?

arXiv:2606. 04023v1 Announce Type: cross Abstract: While large language models (LLMs) have been extensively evaluated on code generation tasks for general-purpose programming and GPU-accelerated environments (e.

How Weight Encoding Affects Language Model Placement and Performance on the Apple Neural Engine

The study examines how different weight encodings—dense fp16, int8, and ternary with two‑bit lookup tables—affect the placement and performance of language models on Apple’s Neural Engine (ANE) via Core ML. Using five checkpoints across two architectures, the authors combine compiler plans, memory‑controller measurements, and compute‑unit controls to assess a single‑token forward workload. Results show that fp16 models may run on the CPU or ANE depending on size, while compressed int8 models consistently activate the ANE and halve warm‑forward latency, demonstrating that encoding influences both placement and speed.

Structured Testbench Generation for LLM-Driven HDL Design and Verification-Oriented Data Curation

arXiv:2606. 12983v1 Announce Type: new Abstract: Automated testbench generation has become a critical bottleneck in large language model (LLM)-driven Register Transfer Level (RTL) workflows, where large numbers of candidate designs must be verified rapidly and reliably.