Efficient Controllable Generation for SDXL with T2I-Adapters

Exploring simple optimizations for SDXL

HighTide: An Agent-Curated Open-Source VLSI Benchmark Suite

arXiv:2606. 04126v1 Announce Type: cross Abstract: We introduce HighTide, an evolving AI-assisted benchmark suite.

SDXL in 4 steps with Latent Consistency LoRAs

Accelerating SD Turbo and SDXL Turbo Inference with ONNX Runtime and Olive

LP5X-PIM Sim: A High-Fidelity HW/SW Integrated Simulator for LPDDR5X-PIM

arXiv:2606. 00636v1 Announce Type: cross Abstract: This tech note describes the architecture and execution results of the LPDDR5X-PIM simulator, developed by Samsung Electronics.

QiMeng-ChipV-RTL: Exploiting Information Locality for IP-level Verilog Generation

QiMeng-ChipV-RTL is a multi‑agent framework that tackles the challenges of generating Register‑Transfer Level (RTL) code for industrial IP‑level hardware design. By partitioning long design documents into short, localized tasks and using hierarchical planning, localized code generation, interface‑consistent merging, and AST‑guided debugging, it scales to complex specifications. Experiments on the RealBench benchmark show ChipV-RTL achieves a 45.0% pass rate, outperforming state‑of‑the‑art LLMs and agents which reach only 21.6%.

Can Agents Design Better Chips with a Higher Level Abstraction?

Large Language Model agents are being explored for chip design, but most methods work directly at RTL. This study compares Direct RTL Design, Agent-based HLS Design, Post-Compiler HLS Refinement, and Post-HLS RTL Refinement, and proposes a combined workflow called Agent-based HLS with RTL Refinement (AHRR). Using FPGAs for evaluation, AHRR achieves a 2.6× geometric‑mean speedup over Direct RTL Design across an 11‑task benchmark suite, demonstrating that higher‑level abstractions and subsequent RTL refinement can improve chip design efficiency.

Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement

arXiv:2606. 19387v1 Announce Type: cross Abstract: Large language models (LLMs) have achieved remarkable success in software development.

OctoNest: Adaptive Cross-Device Execution through Stateful Control

arXiv:2606.20487v2 Announce Type: replace Abstract: Computer use agents are expanding from single-device operation toward cross-device systems that coordinate tasks across heterogeneous environments....

Large Language Model for Verilog Code Generation: Literature Review and the Road Ahead

The article reviews the growing use of Large Language Models (LLMs) for generating Verilog code, a key hardware description language in electronic design automation. It surveys 102 papers, covering conferences, journals, and preprints, and addresses four research questions about LLM selection, datasets, techniques, and alignment strategies. The review identifies current limitations and proposes a roadmap for future research in LLM-assisted hardware design.

Alpha-RTL: Test-Time Training for RTL Hardware Optimization

arXiv:2606. 05253v1 Announce Type: new Abstract: Large language models (LLMs) have shown increasing promise in generating functionally correct register-transfer-level (RTL) hardware designs.

20x Faster TRL Fine-tuning with RapidFire AI