arXiv:2607. 22869v1 Announce Type: cross Abstract: Monte Carlo tree search (MCTS) enables artificial intelligence (AI) decision-making, but requires 55-300 W on conventional processors, limiting edge deployment.
Machine-generated by The Flow from the publisher's headline and feed description — not written or checked by a human. The full article lives at arXiv AI.
arXiv:2604. 26968v2 Announce Type: replace-cross Abstract: Key-value (KV) cache memory management is the primary bottleneck limiting throughput and cost-efficiency in large-scale GPU inference serving.
arXiv:2606. 02781v1 Announce Type: cross Abstract: Deep neural networks (DNNs) have achieved state-of-the-art performance across diverse domains.
arXiv:2505. 14303v3 Announce Type: replace-cross Abstract: Using Resistive Random Access Memory (RRAM) crossbars in Computing-in-Memory (CIM) architectures offers a promising solution to overcome the von Neumann bottleneck.
arXiv:2607. 26491v1 Announce Type: cross Abstract: The energy consumption of Large Language Model (LLM) serving is becoming a major system challenge as deployment scales, driven by hardware power and thermal constraints and rising electricity costs.
RACE-AIMC is a framework that selects a single analog in‑memory computing (AIMC) accelerator from a pool to meet a specified energy budget while providing a mathematically exact upper bound on its error rate. Offline, it evaluates each chip, chooses the best one, and computes the bound; online, only that chip runs and a lightweight check decides whether to accept its output or defer to a fallback. Simulations show the certified error stays below 10% (mean 7.83%) and the system achieves clean‑digital accuracy while reducing energy use by about 69% compared to running all chips.
arXiv:2607. 05240v1 Announce Type: cross Abstract: Computing-in-Memory (CIM) accelerators execute Matrix-Vector Multiplications (MVMs) in memory, making them a compelling solution for Machine Learning (ML) workloads.