BRIDGE-EEG is an efficient multi‑task EEG classification pipeline that leverages self‑supervised pretraining while dramatically reducing model size. It maps heterogeneous EEG recordings to a unified 62‑channel time‑frequency representation, pretrains an SE‑ResNet18 teacher with SimCLR, and distills it into smaller SE‑ResNet8 and SE‑ResNet4 students. The compact models achieve accuracy comparable to or better than larger foundation models on abnormality detection and emotion recognition, and they consume up to three times less energy on edge devices, enabling deployment on wearable hardware.
By Meghna Roy Chowdhury, Chengwei Zhou, Haotian Yu, Gourav Datta, Shreyas Sen
arXiv:2602. 07400v2 Announce Type: replace Abstract: Gradient-based LUT- and logic-gate-based neural networks (LUTNet, LogicNets, DiffLogic, PolyLUT, NeuraLUT, WARP-LUT, DWN, LILogicNet, LightLUT) replace multiply-accumulate arithmetic with Boolean lookups.
By Simon B\"uhrer, Andreas Plesner, Aczel Till, Roger Wattenhofer
arXiv:2607. 08427v1 Announce Type: cross Abstract: Achieving nanosecond-scale inference latency for deep neural networks (DNNs) has become a primary architectural concern for latency-critical applications.
By Jiawei Liang, Haotong Qin, Linfeng Du, Xingyu Liu, Shangkun Li, Hui Yu, Michele Magno, Xinyu Chen, Jiang Xu, Wei Zhang
Achieving nanosecond-scale inference latency for deep neural networks (DNNs) has become a primary architectural concern for latency-critical applications. While Field-Programmable Gate Arrays (FPGAs) offer a promising substrate for low-latency inference, conventional FPGA accelerators remain arithmetic-centric, using LUTs primarily as building blocks for numerical operators and peripheral logic.
arXiv:2606. 08594v1 Announce Type: new Abstract: Deep learning EEG denoising architectures have scaled from tens of thousands to tens of millions of parameters, yet no prior study has isolated model capacity as the experimental variable or tested whether reconstruction metrics predict downstream neural-signal utility.
By Jasmeet Singh Bindra, Siddharth Panwar, Shubhajit Roy Chowdhury
XLOG is a CUDA‑native logic programming engine that fuses neural perception with deterministic Datalog, probabilistic inference, and epistemic world views. It offers multiple reasoning modes that share device data planes, with host‑orchestrated Datalog and exact inference, and resident recursive and Monte Carlo cores that avoid host‑device transfers. The system supports end‑to‑end gradients through GPU knowledge compilation, achieves significant speedups in MNIST‑addition training and join operations, and demonstrates competitive accuracy on several benchmark tasks.
By Levi Dubrovin, Nikita Pospelov, Kirill Sabitov
arXiv:2608. 07033v1 Announce Type: new Abstract: This work investigates whether Electroencephalograph (EEG) foundation models (EFMs) can be made faster and locally deployable without sacrificing accuracy.
By Lingwei Li, Yirong Kan, Peng Chen, Xu Cao, Zheng Chen, Yasuhiko Nakashima
arXiv:2606. 19964v1 Announce Type: new Abstract: Tsetlin Machine (TM) is a logic-based machine learning approach that relies on simple bitwise operations and finite-state automata, which makes it attractive for edge AI deployments.
By Chanda Gupta, Sanidhya Bhatia, Shaurya Priyadarshi, Himani Panwar, Rishad Shafik, Sudip Roy
arXiv:2607. 05590v1 Announce Type: cross Abstract: Implantable brain-computer interfaces require on-node spike sorting to reduce telemetry bandwidth and power while maintaining reliable neural decoding.
By Binyi Ren, Luca M. Meyer, Majid Zamani
arXiv:2607. 09399v1 Announce Type: cross Abstract: We introduce a novel method for both partial and full optimization of the connections in deep differentiable logic gate networks (LGNs) and lookup table networks (LUTNs).
By Wout Mommen, Lars Keuninckx, Matthias Hartmann, Werner Van Leekwijck, Piet Wambacq
arXiv:2606. 18816v1 Announce Type: cross Abstract: Hybrid brain-computer interfaces (BCIs) that integrate motor imagery (MI) and steady-state visual evoked potentials (SSVEP) provide high-dimensional neural decoding but typically exceed the computational limits of embedded hardware.
By Gourav Siddhad, Yogesh Kumar Meena
arXiv:2606. 17249v1 Announce Type: cross Abstract: The dominant trajectory of modern machine learning has been to scale up: larger models, larger accelerators, larger memory budgets.
By Emre Can Kizilates