arXiv AI
Jun 16
LLM4RTL: Tool-Assisted LLM for RTL Generation
arXiv:2606. 15500v1 Announce Type: cross Abstract: Large language models (LLMs) have facilitated impressive progress in software engineering, code generation, tooling, and systems.
An Unofficial FastLAS Tutorial: A Programmer's Guide
arXiv:2607. 23557v1 Announce Type: cross Abstract: FastLAS is a scalable system for Inductive Logic Programming (ILP): you give it some background knowledge, a language bias, and a set of examples, and it searches for a set of logic program rules (a hypothesis) that explains the examples.
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arXiv Machine Learning
Jul 21
LogicIF: Towards Complex Logic Instruction Following
arXiv:2508. 09125v3 Announce Type: replace-cross Abstract: Instruction following has catalyzed the recent era of Large Language Models (LLMs) and is the foundational skill underpinning more advanced capabilities such as reasoning and agentic behaviors.
arXiv AI
Jun 26
An Empirical Study of LLM-Generated Specifications for VeriFast
arXiv:2606. 26490v1 Announce Type: cross Abstract: Static verification tools can assure industrial scale software, but require significant human labor to write specifications.
arXiv AI
Jul 22
FVRuleLearner: Operator-Level Reasoning Tree (Op-Tree)-Based Rules Learning for Formal Verification
arXiv:2604. 03245v2 Announce Type: replace-cross Abstract: The remarkable reasoning and code generation capabilities of large language models (LLMs) have recently motivated increasing interest in automating formal verification (FV), a process that ensures hardware correctness through mathematically precise assertions but remains highly labor-intensive, particularly through the translation of natural language into SystemVerilog Assertions (NL-to-SVA).
Hugging Face Trending Papers
3d ago
Silinx: An Open, Browser-Based HDL Design Platform for Teaching Digital Systems on FPGA Boards
Silinx is a free, browser‑based HDL design platform that preserves the familiar Xilinx ISE Project Navigator workflow while eliminating the need to install legacy tools. It supports VHDL, Verilog, C/C++ via HLS, schematic and diagram inputs, and generates HDL automatically. Designs are simulated, built, and programmed onto real Spartan‑3E and Spartan‑6 boards over WebUSB, with an open flow that matches ISE’s bitstreams and even outperforms ISE in resource usage and timing for many designs.
arXiv AI
Jul 24
Explaining Weather Bulletins via ILP
arXiv:2607. 21184v1 Announce Type: new Abstract: Inductive Logic Programming (ILP) originated within the Logic Programming community in the Nineties as a framework for combining symbolic learning with declarative knowledge representation.
arXiv AI
Aug 11
Effect of Abstractions and Prompting Strategies on LLM-Guided High-Performance Optimizations
arXiv:2608. 08085v1 Announce Type: cross Abstract: Code performance optimization is a vital aspect of modern software development, as it enables faster response times and reduced resource usage.
arXiv Machine Learning
Jul 28
Benchmarking LLMs for Verilog Design Flows
arXiv:2607. 22759v1 Announce Type: cross Abstract: Large language models (LLMs) show promise in code generation, but their capabilities to produce correct, synthesizable hardware description language (HDL) code still remain to be properly benchmarked.
arXiv Machine Learning
Jun 24
Not All Invariants Are Equal: Curating Training Data to Accelerate Program Verification with SLMs
arXiv:2603. 15510v2 Announce Type: replace Abstract: The synthesis of inductive loop invariants remains a critical bottleneck in automated program verification.
arXiv AI
Jun 4
AlgoVeri: An Aligned Benchmark for Verified Code Generation on Classical Algorithms
arXiv:2602. 09464v2 Announce Type: replace-cross Abstract: Vericoding refers to the generation of formally verified code from rigorous specifications.
arXiv Computation and Language
Sep 10
TreeThink: A Modular Tree Search Library for Mathematical Reasoning with LLMs
TreeThink is an open‑source Python library that provides modular, fully asynchronous tree search for neural theorem proving. It integrates established tree‑search methods with vLLM inference pipelines and supports a range of node evaluation techniques, from lightweight heuristics to neural evaluators. The library connects directly to the REPL servers of Lean 4, Rocq, and Isabelle/HOL, enabling real‑time verification and proof‑state extraction, and it has been evaluated on miniF2F and MATH500, achieving up to an 8.0× wall‑clock speedup from asynchronous execution.
arXiv AI
Jun 15
Protean Compiler: An Agile Framework to Drive Fine-grain Phase Ordering
arXiv:2602. 06142v3 Announce Type: replace-cross Abstract: The phase ordering problem has been a long-standing challenge since the late 1970s, yet it remains an open problem due to having a vast optimization space and an unbounded nature, making it an open-ended problem without a finite solution, one can limit the scope by reducing the number and the length of optimizations.